TimeQuest: how do i set_max_skew at lower hierarchy levels?

[Altera_Forum]

I've written a module which has an input port requiring a max skew constraint. 

I.e. i have to constrain the skew on that port to all registers it feeds.  The following command will only work if my module is the top level entity:  set_max_skew -from [get_ports DATA_IN] 0.200  But it is supposed to be part of an SOPC, and its ports are, well, no longer ports, for they get connected to other modules inside the SOPC. The path to the "port" in question is as follows:  NIOSII:inst1|Foo:the_Foo|DATA_IN  What should i put into my top level (or Nios) .sdc file to constrain this input?  Using Quartus II 9.0.

[Altera_Forum]

Can you explain why you're using a max skew constraint? Probably the only major real use for an input is when a signal comes in from an asynchronous source and the design over-samples it with registers clocked by different phases of a clock. I've never seen anything done like that internally, and want to make sure you're using it right. Otherwise, find the register that now drives that port and do: 

set_max_skew -from [get_keepers REGISTER_NAME_HERE] 0.2

[Altera_Forum]

Exactly. :) This constraint has zero practical sense right now, i'm just testing a receiver with oversampling. Its DATA_IN actually WILL be a top level port in the end. I asked the question to improve my understanding of things... 

Thanks.

[Altera_Forum]

Glad you know it. Note that 0.2ns is really tight. TimeQuest models on-die variation into skew analysis, which tends to be pretty large(I would argue too large at times, but you have to follow the model). So even if two paths were laid out perfectly identical, they would have a decent amount of skew. Naturally, things won't end up being perfectly identical. 

Also, I find to get the best skew, hand-placement is sometimes necessary. The reason is that the placer always tries to put things as close as possible, i.e. it wouldn't put things further away to meet hold timing/skew requirement. It's the router that adds delays for these constraints. So if you're skew constraint was from an input to 8 registers, the placer might put two of the register in the LAB right next to the I/O, then two further away, etc.(I'm only putting two per LAB if they have different clock sources, as there are a limited number of clocks per LAB). That ends up with pretty bad placement as far as skew goes, and it's up to the router to add delay to fix it. It's pretty hard to balance this out. By hand-placing them equidistant, you can get better results. Definitely requires a test design and some elbow grease.