01-09-2018 07:57 AM
Hi,Setup time and Hold time need to be met. If it is not met it is highlighted in red. http://quartushelp.altera.com/15.0/mergedprojects/analyze/sta/sta_about_sta.htm https://www.youtube.com/watch?v=bfmthlz3dgs Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation)
01-09-2018 12:09 PM
--- Quote Start --- Setup time and Hold time need to be met. If it is not met it is highlighted in red. --- Quote End --- The present problem is probably that the OP didn't enter any timing constraints. You get an idea what TimeQuest is assuming if you look at the clocks and unconstrained paths categories in the report. Without any constraints, TimeQuest assumes a default clock frequency of 1000 MHz which makes all timing paths fail. Learn how to apply timing constraints according to your actual design parameters.
01-09-2018 01:00 PM
Hi,Is your design purely combinational one or sequential (clocked)? If its combinational one, you need to specify the IO constraints, max delay, etc. If its a clocked design, you need to specify the clocks, false paths, multi-cycle paths, IO delays, etc. Running the entire flow without specifying any constraints is akin to un-constrained synthesis and PNR, and can cause issues . Make sure you specify the design constraints in the SDC file or use the tool to specify it.