Timequest: Asynchronous feedback from output to input

[Altera_Forum]

Dear Forum, 

 I have some (may be too little) experience with Timequest, but now have a problem with an output register. That signal leaves the FPGA, goes through an aynchronous logic outside the FPGA and enters the FPGA as input and is clocked into an input register .   How do I specify a constraint for that situation ? FPGA design is synchronous with one clock for input and output registers.   Knowing that for example the maximum delay outside the FPGA is t_Extdelay, how do I specify a constraint saying that:   tco(FPGA) + t_Extdelay(external) + tsu(FPGA) has to match the clock period.   Many thank for an advice   Best regards   Juergen

[Altera_Forum]

There is no way to do this with a single constraint, so you are going to need to do some manual budgeting. For example, you can assume the Tsu and Tco are the same and then budget: 

 tsu = (period - ext_delay) / 2 tco = (period - ext_delay) / 2  Then you can use:  input delay = period - ext_delay - tco output_delay = period - ext_delay - tsu  Off course, assuming tsu == tco doesn't make sense, so you can come up with a better number of you do an experiment run to see what a realistic Tsu/Tco is. In your case, you probably want the registers on the I/Os, so it should be easy to test what the timing should be.  Note that another solution is to use set_max_delay/set_min_delay to enter your budgeted delays.  Don't forget to do the same for your min timing (Min Ext Delay, Th and Min Tco)  Also note that if you need to be absolutely sure the timing is met, you will need to change your SDC file after the fit, and use the exact numbers. You can use report_timing (or get_timing_path if you want to script it all) to get the exact numbers, and then enter them in the SDC and then do the true sign-off timing analysis run.   Hope this helps.  -David