Timequest: WHY?

[Altera_Forum]

Sincery I cannot understand why Altera wanna loose the best advantage that it has with its competitors: the integrated quartus II features! 

 I mean: I understand that Timequest is very beautifull and that you can constraint things that you'll never dream about, but in a complex project it's a nightmare!  1- It's almost impossible to find all the net/registers that you want!  2- Write sdc is not usable because it write all the constraints in a file but it's sums up all the others .sdc you've in the project (if you've a Nios with a Triple Speed Ethernet and a DDR2 Controller as it's my case it's a nightmare to find the net and give in the sdc the name its expect - of course the sdc are to be configured because of course timequest do not have a clue about project hierarchy)  3- Design partition with the constraint became a nightmare too  In reality the best way you can use Timequest is use the "old classic time compilator" where you can simple right click on a flip flop or a net you've in a design and give the constraint and then make automagically let quartus revert the constraint in a sdc. After that you can give your difficult constraint such as multicycle and all others.  4- Let's we speak about the fact that for timequest all clock are related? Why the hell it should be! If you've 4 clock all of them entering in 4 different PLL you've to set up all clock groups - exclusive telling it that clocks are unrelated among them..   CONCLUSION: Really after 1 month that I use it, I'm really starting to think that now it's really the same using altera or xilinx if I've to use Timequest (in the end you've to constraint all things manually).  Once Xilinx will finally copy Altera schematic entry and simulator really I think that Altera loose its best advantage over the competitors and in that case only the one that sells devices at lower price will win "the fight" (whereas now I consider Quartus II as a very important plus over Xilinx ISE, because project timeline are easily respected with Altera)  Sorry about all the complaint but really this Timequest shall be better integrated in quartus and shall be an option and not a requirement at least untill it's became usable (yes I'm on a Stratix IV device and I MUST use Timequest..)

[Altera_Forum]

I was in your same boat until I took the Altera Timing Analysis training last week. Now I understand Timequest and realize it is easier to use and much, much more powerful than the classic timing analyzer.  

 Do yourself a favor and go take the training. It is just a different way of doing things and you will quickly realize it is also better. Altera's problem (in general, not just for this) is that their documentation is not the best. You could try the online training, I haven't taken it but it might help.  http://www.altera.com/education/training/courses/odsw1115 (http://www.altera.com/education/training/courses/odsw1115)

[Altera_Forum]

Ouch. I would argue that TimeQuest is much better for complex designs, and a lot of them would have been impossible with Classic TAN. I think one of the simpler arguments is just the fact that TAN didn't have a report_timing command, so if the path you wanted to look at wasn't the worst case, you had to list thousands or tens of thousands of paths and sort through them. That alone makes me cringe whenever I have to work with the Classic TAN. 

But rather than debate it, I'd rather see if there's anything to make your current experience better. Some thoughts: 1) In TimeQuest, use View -> Name Finder. This pops up the window for searching on nets/registers. You can start out with pretty broad wildcards to see what it finds, and then start narrowing it down. (TAN didn't have any special tools for this either, unless you mean right-click locate to Assignment Editor) 2) This concerns me, as I NEVER use write_sdc. Your .sdc file should be a text file that you enter everything into. If you use write_sdc to try and overwrite it, you lose all the niceties of your own syntax, your own comments, your own organization, etc. (And pretty much never use the Constraints pull-down menu in TimeQuest, which would then require you to write out the .sdc file from TimeQuest. Instead, open the .sdc file from TimeQuest's text editor, put the cursor where you want to add a constraint, and go to Edit -> Insert Constraint. You'll have access to the same commands, but under your guidance. (When TimeQuest first came out, Altera was recommending that whole Write SDC flow, and it was a mess. I hated the tool doing that too...) 3) I'm not following the problem. Are you finding registers in the RTL viewer and then making assignments to them?  4) Just because a clock comes in a different pin, doesn't mean it's not related(the DQ clock coming back into the FPGA is a good example.) That being said, I get what you're saying, as TAN's assumptions were right 95% of the time(although the 5% it was wrong caused lots of problems.) Here's what I do once I have clocks in the system(most from derive_pll_clocks). I open TimeQuest and double-click on Report Clocks. I copy all the clock names from the first column and paste them into my .sdc. I then fit them into the following syntax: set_clock_groups -asynchronous   -group {     }   -group {     }   -group {     }  I then just paste clock groups into each group to get the groupings I want. It takes about 5 mintues and then its done. If there are clocks I'm not sure about(like all the DDR2 clocks created for you) I leave them out so they're related to everything, and then resolve any specific clocks if they show up(but usually they do not). Make sure every line but the last ends with\. You can have as many -groups as you want. A clock can only be in one -group per assignment. Any clocks not in this will be related to all clocks.   I personally think Altera would be in a lot of trouble if they hadn't come out with TimeQuest, and know many users who think it's the number one software advantage for using Altera, so please post any gripes/issues or file SRs. That doesn't mean I don't know users who dislike TimeQuest, as it can be complicated for complicated interfaces, and it's easy to make mistakes(where TAN often hid mistakes and let users continue).

[Altera_Forum]

Thanks you for your answer. 

Some of the tricks you've given were nice to know - in the specific in the sdc "editor" - (all the others I've found them all the guide here in Altera forums).  The most think that I miss from Classic Time Analiser is the ability to right click on a part of the schematic entry or on a name in the vhdl files and can add constraint without looking all over with the netlist with the View->NameFinder (REMEMBER TO CLICK the HIERACHY tick to look into all the design).  Moreover another important thing is the -asyncronous I've used the -exclusive that work in the same manner but with only 2 groups each time.. So I've done a lot of constraint for this issue (didn't know the -asyncronous and neither the FAE that I've asked it..) I suggest if you can to edit the "TimeQuest CLocks Quick Start Guide" that you've posted here on the Altera forum (link: http://www.alteraforum.com/forum/showthread.php?t=790&highlight=timequest+clocks+quick+start+guide).  Maybe put it as a Sticky post together with the others guide you've done very well such as: - http://www.alteraforum.com/forum/showthread.php?t=1845&highlight=timequest+clocks+quick+start+guide  - http://www.alteraforum.com/forum/showthread.php?t=5026&highlight=understanding+recovery+removal+analisys  I found them very usefull.  Thx a lot for your suggestions and job

[Altera_Forum]

Actually, I've found out that -exclusive and -asynchronous do the same thing in TimeQuest, they cut timing between clocks in separate groups. The difference is from ASIC land, in that -exclusive means they won't toggle at the same time, and would be used for two clock assignments on the output of a clock mux, or maybe two different clocks that could potentially come in on the same pin. Knowing they won't toggle, the IC tools know there won't be any inter-action such as cross-talk. (Hardcopy designs use this too). In FPGAs they give the same results, although I should change that to -asynchronous since I think it makes more sense. (Personally I would like to re-do a lot of this and make it all flow together.) 

One thing I do, although it's not quite as straightforward, is right-click on a name like you have been doing and Locate -> Assignment Editor. Then I just copy the name from there, so I have the full hierarchy, and use it in TimeQuest(including Name Finder to verify it's correct.) If not using the Name Finder and just putting it into a command in my .sdc directly, put it in curly brackets to match the name exactly as entered. Since I don't let Quartus/TimeQuest enter constraints for me anyway, that's the best approach I've found.

[Altera_Forum]

I've got to agree with the others as well. There is definitely a learning curve with TimeQuest. However, once I overcame that learning curve I totally fell in love with it. It is far superior to the classic timing analyzer and I know the quality of my timing constraints has improved. 

With the classic timing analyzer, it was far to easy for the engineer to pretend he had properly constrained his design whether he had or not.  Jake

[Altera_Forum]

I just add some informations I've came across while constraint my desing. 

 About "set_clock_groups -asynchronous" vs "set_clock_groups -exclusive" what Rysc told is perfectly right. In FPGA Timequest treat both in the same way. The only thing usefull is that with -asyncronous parameter you can set more than 2 clock groups together, whereas -exclusive is limited to maximum of 2.  Another syntax problem I came across (because I didn't find explained on Altera documentations) is the the TCL backslash use. It's used in order to make a command continue on next line because in tcl all command are closed on the line or by a ;. There is an important exception that are the use of {}. When you use { the command is not closed untill it find } so for example the correct syntax of set_clock_groups reported above shall be  set_clock_groups -asynchronous  -group {   clk1  clk2 }  -group {   clk3  clk4 }  -group {   clk5 }  so you need only the \ outside the curling brackets. That's the same also when you use the double quotes " instead of curling brackets. The difference is that if in "" you find a $var_name that will be substituted.  Example: set a pippo  puts "my names is $a" -> my names is pippo  puts { my names is $a }  -> my names is $a

[Altera_Forum]

Note that the backslash has nothing to do with .sdc syntax, exactly, but is a function of Tcl. It's the escape character, and when put at the end of a line, escapes that eol character. (I've always put the escape after every clock in the group, but I like your syntax better).

[Altera_Forum]

Hello everyone: 

 I have a DK-DSP-3C120N kit.Recently,I'm struggling with the DDR2 HP Controller under the direction of AN517(Using High-Performance DDR, DDR2, and DDR3 SDRAM With SOPC Builder).The design is targeted to the Cyclone® III EP3C120F780C7 Kit.  In this example,the SOPC system contain a Half-Rate DDR2 Controller working at 150MHz(altmemddr_auxfull),the PLL of the controller simultaneously generate a 75MHz output clock(altmemddr_sysclk) which been used as SOPC system clock.  After compilation,I got three critical warning,cause by JTAG.The TimeQuest report negative slack(-2.435) in Summary(Removal) of altera_reserved_tck. The Top Failing Paths (Removal:altera_reserved_tck) is this: Slack:-2.435 From---altera_reserved_tck  To-----pzdyqx:nabboc|pzdyqx_impl:zdyqx_impl_inst|FNUJ6967  I've tried to slow the DDR2 clock down to 133.333MHz,the NIOS clock down to 66.667MHz,but the slack value still negative.  I lose my head of this because I've constrained the JTAG using the templet:# JTAG Signal Constraints constrain the TCK port create_clock -name tck -period 100.000 [get_ports altera_reserved_tck]# Cut all paths to and from tck set_clock_groups -asynchronous -group [get_clocks altera_reserved_tck]# Constrain the TDI port set_input_delay -clock altera_reserved_tck -clock_fall 1 [get_ports altera_reserved_tdi]# Constrain the TMS port set_input_delay -clock altera_reserved_tck -clock_fall 1 [get_ports altera_reserved_tms]# Constrain the TDO port set_output_delay -clock altera_reserved_tck -clock_fall 1 [get_ports altera_reserved_tdo]  I didn't know what's wrong with it. Can anybody help me? Thank you very much!