Timing Analysis Issue

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

Timing Analysis Issue

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I am using Cyclone IV GX with Quartus 14.0 to create a simple DSP system.

I have simulated my design, which looks good however I am having issues after programming so I constrained the design.

However the timing analysis after building throws up an issue.

I get a setup slack of -8.5ns for the nodes of an ALTSHIFT_TAPS block with a ALTPLL output c1 as the launch and latch clock.

The PLL is driven by a 12.288MHz clock and multiplied by 8 to give a C1 of 98.304MHz.

The PLL is in the top block and this drops down one block into a DSP module that has the ALTSHIFT_TAPS function.

There is a second ALTSHIFT_TAPS in the design which is configured the same way and throws up no such issue.

Anyone any ideas as to what is wrong or what can be done to fix this?

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