Timing Error with RGMII CycloneV SoC

Altera_Forum · ‎12-08-2015

Hi. I'm "720_com" of Altera beginner.

I want to solve the timing violation message.

Design : Cyclone V RGMII Example Design

http://rocketboards.org/foswiki/view/projects/cyclonevrgmiiexampledesign

I found same topics. But, there is no writing it.

http://www.alteraforum.com/forum/showthread.php?t=50845

So, I'm in trouble.

Setup Timing violation path : TX_CLK_OUT_125

I am trying the below( 9 paths);

http://www.alteraforum.com/forum/showthread.php?t=46960

It is look like timing violation.

I want solve timing error. Please tell me about solve it.

If anyone has any idea, please tell me.

Thanks in advance.

Altera_Forum · ‎12-12-2015

i think your file is in 15.0? i thought the design was tested in 14.0. maybe a short one... you revert to 14.0 and try to compile this at lease once just to confirm if the proven version work on your side.

Altera_Forum · ‎12-14-2015

Thank you for your answer.

I tried compilation, but it occured timing error, too.

Please give me your design.