Hello all,
I am looking for some help trying to close the timing for a new design.
I need to inferface a Cyclone V E A5 with an ADC (AD9484). The ADC digital output is synchronous SDR at a 405Msamples/s rate, and it is provided through parallel LVDS channels, that is, 1 LVDS channel for every bit (8 bits-8 LVDS channels), and an edge aligned LVDS clock output.
I feed a PLL with the edge aligned clock to generate a 180° shift clock that allows me to sample the data at its center. For this purpose I use the ALTLVDS_RX core. Besides, this generated clock drives a small portion of logic, just some basic control as the number of aquired samples, decimation factors, etc... I have configured the PLL in source-synchronous mode (I have also tried before in lvds mode) and it looks to be fine for the acquisition stage. But I cannot close the timing for the additional control logic, and I wonder if I should use a second PLL in normal mode to clock this part, although it seems really odd to me.
I think I should not have these problems to drive such a small part of logic at 405MHz, and so I think I must be doing something wrong.
Do you have any idea?
Thanks a lot in advance!!
