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Altera_Forum
Honored Contributor I
1,135 Views

Timing parameters of USB Blaster 1

I'd like to constrain the timing of the JTAG interface of my Arria 10 design for a USB Blaster Rev C (note: not USB Blaster II). However, the documentation doesn't mention any details about the timing like clock to output and cable delays. Where can I find these parameters?

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Altera_Forum
Honored Contributor I
84 Views

What are you hoping to achieve by constraining the JTAG interface? I assume you're referring to the TCK, TMS, TDI, TDO pins on the device... 

 

The JTAG logic inside the device is fixed and not influenced by place and route. The JTAG timing is specified in the documentation, along with relative timing, which your JTAG host must adhere to. This is true regardless of USB-Blaster type of third party kit. Constraining the interface will not tell you whether the design meets the timing specified in the datasheet - it just will. 

 

Unless you're talking about a JTAG interface into your logic, in which case you'd be using a user clock which you must constrain as normal. 

 

Cheers, 

Alex
Altera_Forum
Honored Contributor I
84 Views

I want to ensure that JTAG timing is met when there is a Signaltap instance in the design. From the timequest timing analyzer cookbook (https://www.altera.com/documentation/mwh1452708879095.html#mwh1452708874207): 

 

 

--- Quote Start ---  

Many in-system debugging tools use the JTAG interface in Altera FPGAs. 

When you debug your design with the JTAG interface, the JTAG signals TCK, TMS, TDI, and TDO are implemented as part of the design. Because of this, the TimeQuest analyzer flags these signals as unconstrained when an unconstrained path report is generated. [...] You can constrain the JTAG signals by applying the following SDC commands: ...  

--- Quote End ---  

 

 

And then some code follows that apparently uses the timing parameters given in the handbook of the USB Blaster II.  

 

The TDO port, for example, is driven by the Signaltap logic (through the TDOUSER input of the altera_internal_jtag) as far as I can see from the Technology Map Viewer. Or am I getting this wrong?
Altera_Forum
Honored Contributor I
84 Views

 

--- Quote Start ---  

I want to ensure that JTAG timing is met when there is a Signaltap instance in the design. From the timequest timing analyzer cookbook (https://www.altera.com/documentation/mwh1452708879095.html#mwh1452708874207): 

 

 

 

And then some code follows that apparently uses the timing parameters given in the handbook of the USB Blaster II.  

 

The TDO port, for example, is driven by the Signaltap logic (through the TDOUSER input of the altera_internal_jtag) as far as I can see from the Technology Map Viewer. Or am I getting this wrong? 

--- Quote End ---  

 

 

jtag not being part of core logic was not constrained but since quartus Pro things changed (not sure what is going on here). See this link: 

 

 

https://www.altera.com/support/support-resources/knowledge-base/solutions/rd07182016_788.html
Altera_Forum
Honored Contributor I
84 Views

I like the very helpful "Note that the values for tdi_input_delay_*, tms_input_delay_* & tdo_output_delay_* should match the destination hardware." from that Altera support page :rolleyes: 

As a starting point I think you can use the values from an Altera USB Blaster II even if you use an USB Blaster I
Altera_Forum
Honored Contributor I
84 Views

Yes, the USB Blaster II constraints seem to be quite restrictive.

Altera_Forum
Honored Contributor I
84 Views

The problem looks to me as over-engineering. USB Blaster is really slow (6MHz TCK) you have nearly half cycle setup and hold time according to JTAG design principle. 

 

Most real world JTAG problems are caused by insufficient signal integrity and not fixed via timing constraints. 

 

I would expect that even maximum 24 MHz JTAG of USB Blaster II runs safely without timing constraints, but I don't use it yet.
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