Timing paths problem

[Altera_Forum]

hellow every body; 

I made a timing analysis using altera time-quest timing analyzer, and i found that there are many paths that is not belongs to my design and report a timing problems. Is this can be happens in altera timing report. if this can be occurs. is it correct to set these paths as false nodes. Thanks

[Altera_Forum]

All of those paths belong to your design in one way or another, sometimes the names mcan be very cryptic, but they are part ofyour design nonetheless. With a little puzzling you can teace it back to the design entity and then the region in the code where it is described.

[Altera_Forum]

Thanks for ur attention. But what is the meaning of "set false path between nodes"

[Altera_Forum]

Please see: 

http://quartushelp.altera.com/14.0/mergedprojects/tafs/tafs/tcl_pkg_sdc_ver_1.5_cmd_set_false_path.htm or https://www.altera.com/support/support-resources/design-examples/design-software/timequest/tq-false-path.tablet.html  I read a good explanation somewhere a few months ago, but I forgot where it was I read it. It may even have been a post on this very forum.

[Altera_Forum]

IP blocks often have required timing. You must specify timing constraints as needed by any IP you are using. You will find what is required (if anything) in the documentation for the IP blocks.

[Altera_Forum]

--- Quote Start ---  IP blocks often have required timing. You must specify timing constraints as needed by any IP you are using. You will find what is required (if anything) in the documentation for the IP blocks.  --- Quote End ---    Here's the best application note I've found on these things: https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/an/an545.pdf