Hi,
I am trying to use a megacore fifo, and in the verilog file trying to include the altera_attribute to control the synthesis option for embedded constrain.
(* ALTERA_ATTRIBUTE = “-name SDC_STATEMENT set_multicycle_path -end -setup -from [get_registers *|REG1] -to [get_registers *|REG2)
When I read through the user guide page 66 and 67 (attached)
I found that this attribute had to be written manually after the megacore fifo generated (correct me if I was wrong)
The question is:
1) Can the Altera attribute or there is other way (may be synthesis option) to control the embedded constrain when simulation compiled? (you may find “Info: Evaluating HDL-embedded SDC commands” after compile)
2) Can we auto generate the Altera attribute when the megacore fifo created in verilog file. (which I doubt it can)
Thanks if there is any one can clarify for me,
Best regards
Tan
