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Altera_Forum
Honored Contributor I
831 Views

To generate Pulse signals with Generic tri-state controller

Hi ! 

 

My task is to generate pulse and trigger signals using Quartus and NIOS Processor. I'm using Generic tri-state controller to communicate with registers in Quartus from NIOS to enable the signals. Registers are below. But in In A_OUT_REG2, i am not getting any value, can anyone go through below code and suggest me.  

 

-- Register Address Map constant A_IN_REG0 : std_logic_vector(7 downto 0) constant A_OUT_REG0 : std_logic_vector(7 downto 0) constant A_IN_REG1 : std_logic_vector(7 downto 0) constant A_IN_REG2 : std_logic_vector(7 downto 0) constant A_IN_REG3 : std_logic_vector(7 downto 0) constant A_IN_REG4 : std_logic_vector(7 downto 0) constant A_IN_REG5 : std_logic_vector(7 downto 0) constant A_IN_REG6 : std_logic_vector(7 downto 0) constant A_IN_REG7 : std_logic_vector(7 downto 0) constant A_OUT_REG1 : std_logic_vector(7 downto 0) constant A_OUT_REG2 : std_logic_vector(7 downto 0)  

 

NIOS Code 

eve_stop_flag = IORD_32DIRECT(HW_LOGIC_BRIDGE_BASE, A_OUT_REG2); / if(eve_stop_flag == 1) { eve_cnt = IORD_32DIRECT(HW_LOGIC_BRIDGE_BASE, A_OUT_REG1); Pac_cmd = 0x00CF; Pac_data = (unsigned short)eve_cnt; Pac_data = (eve_cnt & 0xFFFF0000) >> 16; Pac_size = 2; printf("%d\n",eve_cnt); // Not getting any values udp_Ack_Process(); eve_stop_flag = 0; SW_system_rst(); } 

 

Quartus : VHDL code 

entity logic is port ( RPC_OUT : out std_logic_vector(127 downto 0); TRIGGER_OUT : out std_logic; LCLK : in std_logic; MCU_ADDR : in std_logic_vector(7 downto 0); MCU_nRD : in std_logic; MCU_nWR : in std_logic; MCU_DATA : inout std_logic_vector(31 downto 0); nRST : in std_logic ); end logic; architecture behav of logic is signal RPC_OUT_AUX : std_logic_vector(127 downto 0); signal RPC_OUT_AUX_1 : std_logic_vector(127 downto 0); signal MCU_DINs : std_logic_vector(31 downto 0); signal MCU_DOUTs : std_logic_vector(31 downto 0); signal OUT_REG0s : std_logic_vector(31 downto 0); signal command_reg_0 : std_logic_vector(31 downto 0); signal command_reg_1 : std_logic_vector(31 downto 0); signal command_reg_2 : std_logic_vector(31 downto 0); signal command_reg_3 : std_logic_vector(31 downto 0); signal command_reg_4 : std_logic_vector(31 downto 0); signal command_reg_5 : std_logic_vector(31 downto 0); signal command_reg_6 : std_logic_vector(31 downto 0); signal RPC_OUT1s:STD_LOGIC; signal RPC_OUTs : std_logic_vector(127 downto 0); signal eve_freq : std_logic_vector(31 downto 0); signal eve_cnt : std_logic_vector(31 downto 0); signal RAW_COUNTs : std_logic_vector(31 downto 0); signal Triggers:STD_LOGIC; signal eve_enables:STD_LOGIC; signal trig_enables:STD_LOGIC; signal eve_test_end_flag:STD_LOGIC; MCU_DATA <= MCU_DOUTs when MCU_nRD = '0' else (others => 'Z'); MCU_DINs <= MCU_DATA; ------------------------------------------------------------------------------ -- Read and write to registers ------------------------------------------------------------------------------ process(LCLK, nRST) begin if(nRST = '0') then --LED_OUT(0) <= '0'; OUT_REG0s <= X"44445555"; trig_enables <= '0'; -- Read from registers elsif(LCLK'event and LCLK = '1') then if(MCU_nRD = '0') -- read pulse from CPU then case MCU_ADDR is when A_OUT_REG0 => MCU_DOUTs(31 downto 0) <= OUT_REG0s; when A_OUT_REG1 => MCU_DOUTs(31 downto 0) <= RAW_COUNTs; when A_OUT_REG2 => MCU_DOUTs(0) <= eve_test_end_flag; ///// when others => MCU_DOUTs <= X"FFFFFFFF"; end case; end if; -- Write to registers if(MCU_nWR = '0') -- write pulse from MCU then case MCU_ADDR is --when A_IN_REG0 => LED_OUT(0) <= MCU_DINs(0); when A_IN_REG1 => command_reg_0 <= MCU_DINs; when A_IN_REG2 => command_reg_1 <= MCU_DINs; when A_IN_REG3 => command_reg_2 <= MCU_DINs; when A_IN_REG4 => eve_freq <= MCU_DINs; --notice one offset when A_IN_REG5 => eve_cnt <= MCU_DINs; when A_IN_REG6 => command_reg_5 <= MCU_DINs; when A_IN_REG7 => command_reg_6 <= MCU_DINs; --eve_enables <= MCU_DINs(0); trig_enables <= '1'; when others => NULL; end case; else --trig_enables <= '0'; --LED_OUT(0) <= '0'; end if; end if; end process; ---------------------------------------------------------------------------- ---- pulse generator AIM to Generate PULSE and TRIGGER ---------------------------------------------------------------------------- process(LCLK) variable count1 : std_logic_vector(31 downto 0); variable count2 : std_logic_vector(31 downto 0); begin if(nRST = '0') then count1 := (others => '0'); eve_enables <= '1'; RPC_OUTs <= X"00000000000000000000000000000000"; eve_test_end_flag <= '0'; elsif(LCLK'event and LCLK = '1') then if(trig_enables = '1' and eve_enables = '1')then eve_test_end_flag <= '0'; if(count1 < (eve_freq + 2)) then count1 := count1 + '1'; end if; if(count1 = 1) then RPC_OUTs <= X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"; end if; if(count1 = 3) then RPC_OUTs <= X"00000000000000000000000000000000"; end if; -- generate trigger if(count1 = 15) then Triggers <= '1'; end if; if(count1 = 40) then Triggers <= '0'; end if; if(count1 = eve_freq) -- frequency then count2 := count2 + '1'; count1 := (others => '0'); end if; if(count2 >= eve_cnt) -- event counter then count2 := (others => '0'); eve_enables <= '0'; RPC_OUTs <= X"00000000000000000000000000000000"; eve_test_end_flag <= '1'; end if; end if; end if; end process;
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5 Replies
Altera_Forum
Honored Contributor I
50 Views

Hi Saras,  

 

did you forgot to assign the constants for the addresses? 

 

constant A_IN_REG0 : std_logic_vector(7 downto 0) := X"00"; 

constant A_IN_REG1 : std_logic_vector(7 downto 0) := X"01"; 

 

... 

 

The same you have to use in your Nios program. 

 

 

 

Jens
Altera_Forum
Honored Contributor I
50 Views

Hi,  

 

I have already assigned the constants for the addresses? In Quartus and Nios , but it is not working.
Altera_Forum
Honored Contributor I
50 Views

I have attached the Qsys component model.  

 

https://www.alteraforum.com/forum/attachment.php?attachmentid=15794
Altera_Forum
Honored Contributor I
50 Views

How do you implemented the Tristate Controller? In Qsys? How it is connected to your Toplevel? 

 

For example, I'm using it for connecting an external Flash device to my Qsys. (see attached jpg)
Altera_Forum
Honored Contributor I
50 Views

I think if you use the Tristate-Controller to connect internal logic you also have to add a Tristate-Conduit bridge to the Tristate conduit master port of the controller. 

But for connecting internal logic it is better to use a custom component which can be generated with the Qsys component editor. 

There you need at least one Avalon memory mapped slave port, a clock input and a reset input. 

 

Jens
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