Topic: how shift in(16 bit) and shift out(1 bit at a time)

[Altera_Forum]

Topic: how shift in(16 bit) and shift out(1 bit at a time) 

Example:shiftin[15..0] and shiftout[0]   How to edit the RAM- based shift register(Altshift_taps) megafunction to meet my requirement Currently I am using the RAM- based shift register(Altshift_taps) megafunction, on block diagram

[Altera_Forum]

wouldn't it be easier to just write something in verilog rather than using a megafunction? i.e. 

 reg [15:0] bits;  assign shift_out = bits[15];  always @ ( posedge clk )  if ( load )  bits <= data;  else if ( enable )  bits <= { bits[14:0], 1'b0 }; // or bits <= bits << 1, whichever you prefer.  -Mux