Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
21009 Discussions

Total execution time and propagation delay

Altera_Forum
Honored Contributor II
5,120 Views

hi, 

How to calculate total execution time and propagation delay for VHDL files under Quartus II? 

Thank you
0 Kudos
21 Replies
Altera_Forum
Honored Contributor II
429 Views

You need to read a textbook on digital logic design. Registers are one of the most basic elements.

0 Kudos
Reply