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Hi,
I am using the Altera's free application interface /DMA that comes with PCI Express core. I want to know whether this DMA has completion reordering feature or not? I used my hardware setup with jungo windriver. I am transferring 8Gb data from PC to DDR3 memory(attached on my custom board) using DMA. On one PC I found that the received data has some ordering issue quite frequently. But the strange part is that I am not getting this problem on another PC even after several transfers. Since 8Gb data is quite big I should have problem on the other PC as well. What else can be the issue? Thanks Ali UmairLien copié
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I'd guess that the fpga generates the TLP in address order, however the PC end might generate terminations in a different order from which the requests are generated.
Even snooping the cpu data cache could make a difference.
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