Tri-state bus data bus delayed

[SDavi9]

I have a design where my data bus is tri-stated and everything seems to work correctly till the tri-state buffer. For some reason the output of the tri-state buffer is delayed by a clock from the input ? Could there be some Quartus setting that might be doing this ? 

[SDavi9]

Dear Sheng,

Thanks for getting back to me.

I looked at your test.qar and I am trying to cut down my original design so that we have only the usbD data path - similar to the design files that I sent you - maybe there is something I missed in the design files that I sent you. I realized that I did missed one register that is implemented before the write state machine (I didn't think that this would be relevant as we are interested in the output path of usbD not necessarily the input sources !?). As soon as I have this I will send it to you.

Isn't it strange that the clocked process within the write state machine causes the Quartus Synthesizer to create a register between the output mux and the bi-drectional buffer ?

Best regards

Shmuel 

[ShengN_Intel]

Hi,

Sure. I'll wait for the updated file.

Thanks,

Best Regards,

Sheng