Triple Speed Ethernet: Do I have to edit *_tse_mac_constraints.sdc in a Qsys project?

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Hello, 

 I'm working on a Qsys project where we use a Triple Speed Ethernet Core and I have troubles to correctly constrain my design. Also I'm a beginner when it comes to timing constraints.  When I generate the project in Qsys it will create a sdc-file for the ethernet core (<project_name>__tse_mac_constraints.sdc). According to what's written in the Wiki (http://www.alterawiki.com/wiki/altera_triple-speed_ethernet_timing_contraints_design_example) one hast to edit the timing constraints file. The example projects don't seem to touch that file though (http://www.altera.com/support/examples/nios2/exm-tse-sgdma.html). Additionally the timing constraint file would be regenerated and thus overwritten if the Qsys system gets regenerated.  These are the questions which are currently bothering me: - Do I have to edit the generated timing constraints file? - In the 3c120 triple speed ethernet zip file (qsys) (http://www.altera.com/support/examples/download/niosii-triple-speed-ethernet-3c120-qsys.zip) example there don't seem to be any constraints for the FPGA input and output ports used by the ethernet core whereas in the 4sgx230 triple speed ethernet zip file (qsys) (http://www.altera.com/support/examples/download/niosii-triple-speed-ethernet-4sgx230-qsys.zip) example there are such constraints. Is it good design practice to constrain those ports? If so: why is the 3c120 triple speed ethernet zip file (qsys) (http://www.altera.com/support/examples/download/niosii-triple-speed-ethernet-3c120-qsys.zip) example working reliably then?  Edit: Time Quest Timing Analyzer shows me these warnings: Warning (332174): Ignored filter at qp_sammelplatine_tse_mac_constraints.sdc(155): clk could not be matched with a port Warning (332049): Ignored create_clock at qp_sammelplatine_tse_mac_constraints.sdc(155): Argument <targets> is an empty collection Info (332050): create_clock -period "$DEFAULT_SYSTEM_CLOCK_SPEED" -name altera_tse_${CLK}_$TO_THE_VARIATION_NAME Warning (332174): Ignored filter at qp_sammelplatine_tse_mac_constraints.sdc(158): ff_tx_clk could not be matched with a port Warning (332049): Ignored create_clock at qp_sammelplatine_tse_mac_constraints.sdc(158): Argument <targets> is an empty collection Info (332050): create_clock -period "$FIFO_CLOCK_FREQUENCY" -name altera_tse_${FF_TX_CLK}_$TO_THE_VARIATION_NAME Warning (332174): Ignored filter at qp_sammelplatine_tse_mac_constraints.sdc(159): ff_rx_clk could not be matched with a port Warning (332049): Ignored create_clock at qp_sammelplatine_tse_mac_constraints.sdc(159): Argument <targets> is an empty collection Info (332050): create_clock -period "$FIFO_CLOCK_FREQUENCY" -name altera_tse_${FF_RX_CLK}_$TO_THE_VARIATION_NAME Warning (332174): Ignored filter at qp_sammelplatine_tse_mac_constraints.sdc(162): tx_clk could not be matched with a port Warning (332049): Ignored create_clock at qp_sammelplatine_tse_mac_constraints.sdc(162): Argument <targets> is an empty collection Info (332050): create_clock -period "$TSE_CLOCK_FREQUENCY" -name altera_tse_${TX_CLK}_$TO_THE_VARIATION_NAME Warning (332174): Ignored filter at qp_sammelplatine_tse_mac_constraints.sdc(163): rx_clk could not be matched with a port Warning (332049): Ignored create_clock at qp_sammelplatine_tse_mac_constraints.sdc(163): Argument <targets> is an empty collection Info (332050): create_clock -period "$TSE_CLOCK_FREQUENCY" -name altera_tse_${RX_CLK}_$TO_THE_VARIATION_NAME  So I guess I have to edit the timing constraints file to get rid of these warnings.   Regards Martin