Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
20704 Discussions

Tristating LVDS in Cyclone

Altera_Forum
Honored Contributor II
975 Views

In my design there is a Cyclone with LVDS transmitter that is always powered (in standby) 

The LVDS interface is connected to an LVDS receiver in a STRATIXII device that is not always powered. 

If the LVDS transmitter is powered it will always send a differential '0' or a '1'. I.e. there will always be a voltage on the line (+/-1.4V on LVDS_p referred to GND and +/- 1V on LVDS_n referred to GND). 

Now, if the STRATIXII device is not powered, it will have 1.4V on the LVDS_p line of the receiver. This is not a healthy situtation. Ideally, the LVDS I/Os should be tristated.  

Is there a solution to this problem?
0 Kudos
2 Replies
Altera_Forum
Honored Contributor II
287 Views

I too have not been successful in creating tri-state lvds drivers on the cyclone II's. 

I'm not sure its possible unfortunately.
0 Kudos
Altera_Forum
Honored Contributor II
287 Views

Tristating LVDS is not possible. 

But : In my case it is not necessary because the Stratix II ( and cycloneII too) has the hot socket feature. 

See - http://www.altera.com/literature/hb/stx2/stx2_sii51004.pdf 

■ The device can be driven before power-up without any damage to the device itself. 

 

So, leaving LVDS powered, while the Stratix is not powered is no issue.:D
0 Kudos
Reply