Trouble with Cyclone IV FIFO

[Altera_Forum]

Hello, i use modelsim6.5, i have design with two type of fifos. If i try use simulation there is this error: 

# ** Fatal: (vsim-3420) Array lengths do not match. Left is 8 (7 downto 0). Right is 32 (31 downto 0).# Time: 0 ns Iteration: 0 Process: /tb_toplevel/top_testbench/merici_frontend/gen_fifos__1/fifos/line__47318 File: C:/modeltech_6.5b/win32/../altera/vhdl/src/altera_mf/altera_mf.vhd# Fatal error in Architecture behavior at C:/modeltech_6.5b/win32/../altera/vhdl/src/altera_mf/altera_mf.vhd line 47320  Declaration of fifo is:  dcfifo_mixed_widths generic map ( intended_device_family => "Cyclone IV E",  lpm_hint => "MAXIMIZE_SPEED=5,",  lpm_numwords => 256,  lpm_showahead => "OFF",  lpm_type => "dcfifo",  lpm_width => 32,  lpm_widthu => 8,  lpm_widthu_r => 10,  lpm_width_r => DATA_WIDTH,  overflow_checking => "ON",  rdsync_delaypipe => 3,  underflow_checking => "ON",  use_eab => "ON",  write_aclr_synch => "ON",  wrsync_delaypipe => 3)  port map ( rdfull => rd_fifo_full(i),  wrclk => CLK,  rdempty => rd_fifo_empty(i),  rdreq => fifo_rd_en(i),  aclr => reset,  wrfull => wr_fifo_full(i),   wrempty => wr_fifo_empty(i),  rdclk => CLK,  q => fifo_output(i),  wrreq => pulse_from_sensor(i),  data => cnt_to_fifo(i));  width is 32b for cnt_to_fifo and 8b for fifo_output. I dont know waht is wrong, because width is the same.  If i try use it in the Cyclone II (i change device type) simulation is working with these settings.  Any suggestions?  Thank you, Vaclav