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Trouble with EPCS64

Altera_Forum
Honored Contributor II
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I am working on a custom design using a Stratix II EP2S15 and a EPCS64 as my configuration device.  

 

I am using the Flash Programmer utility to program the EPCS so that it will load my FPGA design and Nios II design on power-up.  

 

The Flash Programmer completes successfully, but when I cycle power the FPGA design runs, but the Nios II design does not.  

 

Any ideas on what steps I may have left out?
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Altera_Forum
Honored Contributor II
618 Views

Hello Gosneja, 

 

I found this solution on Altera's website. Hope it helps: 

 

Why can I not boot a Nios II processor from an EPCS serial configuration device when using a Stratix II FPGA? 

 

http://www.altera.com/support/kdb/solutions/rd03032006_690.html
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Altera_Forum
Honored Contributor II
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Sandyfeet, 

Thank you for the quick response. The link that you sent me definitely sheds some light on what the problem is. However the steps defined do not appear to program the .SOF file into the EPCS device. It seems that it only loads the Nios II design into the EPCS device. Are there steps that it doesn't mention on how to program the .SOF and the new .Flash with offset at the same time?  

 

Thanks for the help!
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Altera_Forum
Honored Contributor II
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Hi, 

 

I think, the older version of Nios II flash programmer allowed for the programming of FPGA configuration in EPCS memories, but the new versions don't. The new versions allow for only cfi flash memory programming for FPGA configuration data even with an EPCS controller instantiated in the system. I think you'll need to program both separately: Use Quartus II programmer to program the .pof file and use the Nios II flash programmer to program the .elf file. May be someone else can suggest a way to program the .pof file in EPCS memory through Nios II flash programmer, if it exists. 

 

Cheers, 

BD
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Altera_Forum
Honored Contributor II
618 Views

Can someone else verify what BD_SLS posted. From what I have read the Flash Programmer still supports programming FPGA Configuration from EPCS devices in version 7.1 

 

Thanks!
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