True Dual Port Ram Synthesizes error with two clock signals

[Altera_Forum]

Hello, 

 well i made a vhdl based, true dual port ram, and i wanted to use two separate clock input for each port, but QuatusII don't synthesizes it and generates the following error  Error: Cannot synthesize dual-port RAM logic "ram"  where 'ram' being : shared variable ram : memory_t; ,  well the problem is that when i use two clocks it gives this error, but when i use single clock, all goes well and i get no error.   any thoughts over this problem?  well the configuration of my system is, that i am using a Cyclone III - ep3c16q240 device, and first i want to test this RAM module alone, and further i will integrate it with my core, and then two different systems will be accessing this RAM with their specific clock. so this is the reason i need two clocks.  will be looking forward for the support. thanks for your time.  regards Ammar

[Altera_Forum]

Reviewing the thread, I see, that up to the middle, every reported issue has turned out as case of effectively operating the RAM in an incorrect way or some basic logic design error. Also considering a learning curve, it seems most likely that we still have something similar, possibly less obvious. Of course, an additional hardware issue would be possible though. Everything can be found out by intelligent utilization of debugging methods, particularly Signal Tap.

[Altera_Forum]

shared variables are not synthesizable