Two LRDIMM (Dual-Rank or Quad rank) support in Arria 10 GX 570 Device

[HBhat2]

Hi,

I am targeting GX 570 device for custom hardware development. There is a need for 2 independent  DDR4 controllers as we are planning to use 2 LRDIMM (Dual or Quad ranks) with Arria 10 GX 570.

As per below link, page 203, GX 570 with NF40 package supports dual LRDIMM with 72 bit interface.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/arria-10/a10_handbook.pdf

Also, page 108 of above link says that, Bank 3A to 3H (8 Adjacent IO banks) are in the same column. By seeing this info, it should be possible to accommodate 2 x72  bit interfaces in GX 570 bank 3A to 3H.

I have started the Quartus compilation for DDR4 pin out verification & the tool is telling that it can not place the 2 controllers due to IO conflict. I am using the "64GB, 2133 CL =15, DDR4 LRDIM" preset for the EMIF controller .

So my question is whether I can place 2 DDR4 x72 memory controllers in a single column from 3A-3G. Or I need to place 1 controller in 3A-3G column & other controller in Bank 2* (2I, 2J, 2K) column?

With Regards,

HPB

[sstrell]

The easiest way to check is to use Interface Planner, assuming you are using the Pro edition of Quartus Prime.  In that tool, you can see exactly what legal locations are available for your interfaces as you place them and get a Tcl script that will automatically set up the required location assignments.

If you're using Standard edition, you can place the interfaces as you want and then run I/O Assignment Analysis to check your placement without having to run a full compilation of the design.  This will be more time consuming because it may require multiple iterations to find a valid placement, but it will get you to a placement solution.

For information on Interface Planner if this is available to you, see this online training:

https://www.intel.com/content/www/us/en/programmable/support/training/course/oblueintro.html

[HBhat2]

Hi,

Thanks for the suggestion with Interface planner.

I found the problem.

As we are placing the EMIF controller in a common I/O column, Need to use same PLL reference clock & reset to both the controllers.

Also, I am using Quartus 18.1 version & it has a known issue as mentioned in the below link.

https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/emif/2019/error-13149---emif-phylite-systems-sharing-a-pll-reference-clock.html
After using same clock for both the controller's PLL ref clk input & applying the work around  I am able to complete the fitter &  able to get the pin out from Quartus. It is mapping the pin outs to IO banks from 3A to 3H.

With regards,

HPB

[HBhat2]

Hi,

I checked in Quartus 20.3 version. 

https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/emif/2019/error-13149---emif-phylite-systems-sharing-a-pll-reference-clock.html

This issue is not yet resolved. I am seeing same issue with latest Quartus version. But If I apply the work around, the compilation with 2 controller is successful. 

What will be the impact of the work around?

With Regards,

HPB

[HBhat2]

Hi,

Any update on the issue @ 20.3 version?

https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/emif/2019/error-13149---emif-phylite-systems-sharing-a-pll-reference-clock.html

What will be the impact of the work around?

With Regards,

HPB

[HBhat2]

Hi,

Any update on this query?

With Regards,

HPB