UART receiving using altera MAX 10

[Tex]

hello,

with the help of few tutorials suggested by forum members i wrote a UART tx and rx code in VHDL 

now the transmission of ascii values is happening but the receiving is not happening i'm stuck at processing the received 10 bits data

the logic is,

when i click "a" the transmission should start 

when i click "z" the transmission should stop 

please go through the code which i mentioned below 

library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity uart_tx_rx is

port ( tclk,clkMCU: in std_logic;
       RX: in std_logic;
       tx: out std_logic;
       debug_pin :out std_logic:= '1';
       debug_pin2 :out std_logic;
       sync:out std_logic;
       sample_clk: out std_logic);
       
end  uart_tx_rx;

architecture arc of uart_tx_rx is

signal counterCLK_counter : integer range 0 to 31;
signal counterRatio : integer := 10;
signal counterClkout : std_logic;
-----------
signal temp : std_logic_vector (0 to 7) ;
------------
signal txClk_counter : integer range 0 to 255;
signal ratio_3 : integer := 10;  
signal txClkout : std_logic;
----------------
signal index : integer range 1 to 10 := 1 ;
signal tx_finish : std_logic := '1';
signal loop_index : integer range 0 to 162 := 0;
signal tx_num : integer range 0 to 7 := 7  ;
--------------------
signal MidSampleCnt_UART   : integer range 0 to 10      := 0;
signal indexUartRx_UART    : integer range 0 to 9    := 0;
signal UARTBufferRx_UART   : STD_LOGIC_VECTOR (7 downto 0):= "00110110";
signal tx_en : std_logic := '1';
signal RxBuf_ready_UART    : integer range 0 to 1     := 0;
--------------

begin
    
    clk_Counter: process(tclk)
    begin

        if rising_edge(tclk) then
            if counterCLK_counter = counterRatio/2-1 then      
                counterClkout <= not counterClkout;
                counterCLK_counter <= counterCLK_counter + 1;
            elsif counterCLK_counter = counterRatio-1 then     
                counterClkout <= not counterClkout;
                counterCLK_counter <= 0;                 
            else
                counterCLK_counter <= counterCLK_counter + 1;
            end if;
        end if;
    end process;        
        
    Counter: process (counterClkout) 
    begin   
        if rising_edge(counterClkout) then 
            temp <= temp + 1;
        end if;     
    end process; 
    
    
    tx_process:process(tclk,tx_en)
    begin
        if rising_edge(tclk) then
            if tx_en = '1' then             
                if (index = 1) then 
                    tx <= '0'; -- start bit
                    index <= index+1;
                    tx_num <= 7;
                elsif (index = 10) then
                    tx <= '1';  -- stop bit
                    index <= 1;
                    tx_num <= 7;    
                else 
                    tx <= temp (tx_num);
                    tx_num <= tx_num-1;
                    index <= index+1;   
                end if;                 
        end if;         
        end if;
    end process;
    
    rx_process:process(clkMCU)
    begin
            if (clkMCU'event and clkMCU = '1') then 
                
                if (MidSampleCnt_UART = 7) then
                    MidSampleCnt_UART <= 0;
                    if (indexUartRx_UART >0) then       
                        UARTBufferRx_UART(indexUartRx_UART-1) <= RX;
                        indexUartRx_UART <= indexUartRx_UART + 1;
                        if(indexUartRx_UART = 9) then   
                            indexUartRx_UART <= 0;
                            --Start (a)
                            if(UARTBufferRx_UART(7 downto 0)= "01100001") then
                                --sampling_en <= '1';
                                tx_en <= '1';
                                --key <= '1';                       
                            end if;
                            -- stop (z)
                            if(UARTBufferRx_UART(7 downto 0)= "01111010") then
                                --sampling_en <= '0';   
                                tx_en <= '0';                   
                            end if; 
                        end if;
                    end if;         
                else
                    if(RX = '0' and indexUartRx_UART = 0) then
                        RxBuf_ready_UART <= 0;
                        MidSampleCnt_UART <= MidSampleCnt_UART + 1;
                        if (MidSampleCnt_UART = 4) then
                            MidSampleCnt_UART <= 0;
                            indexUartRx_UART <= 1;
                        end if;
                    end if;     
                    if(indexUartRx_UART > 0) then 
                        MidSampleCnt_UART <= MidSampleCnt_UART + 1;
                    end if;
                end if;     
        end if;
    end process;
end arc;    

thanks in advance..

Best regards,

Tex

[ShengN_Intel]

Hi Tex,

I had simulated and understood the provide code function. I also made minor modification to the code in order to simulate properly. Check the attached module, testbench and waveform below.

I had assigned clkMCU with the example period of 10ns. Then given RX in '0' (start bit) + "10000110"(reverse of "01100001" ascii: a) and tx_en goes high start transmitting. Based on the code and simulation, the first uart RX index 0 will take MidSampleCnt about 0 to 4 (50ns **x5 clkMCU**) while the rest uart RX index 1-9 each will take MidSampleCnt about 0 to 7 (80ns **x8 clkMCU). Total duration for 1 cycle from index 0 to 9 will be 770ns.

After four cycles, given RX in '0' (start bit) + "01011110" (reverse of "01111010" ascii: z) and tx_en goes low stop transmitting.

Seems like the code provided worked as mentioned. Have you given '0' (start bit) to RX in? Have you ensure that correct timing of each uart RX index from 0 to 9 given to the RX in?

Thanks,

Best Regards,

Sheng

[Tex]

Hello sheng..

I'm honoured to receive your valuable reply,

i just implemented the code which you have sent to me and i simulated it..

i didn't get the proper output please tell me the mistake what i was making.. i attached the image below..

could you please tell me what are the input you have given in simulation..

i given 

clkMCU = 10ns;

tclk = 10ns;

Thankyou,

Best regards,

Tex..

[ShengN_Intel]

Hi Tex,

I had attached the testbench uart_tx_rx_tb.vhd in previous post which included the input given in simulation. Below attached the .zip folder just in case you need it.

Thanks,

Best Regards,

Sheng

[Tex]

Thank you

[ShengN_Intel]

Hi Tex,

You're welcome. Let me know if you have any further concern or update.

Thanks,

Sheng