URGENT: Peripheral to Memory DMA Transaction

[Altera_Forum]

Hello, may I know how to transfer data from peripheral to memory using DMA? It is quite confusing from memory-to-memory transfer. please help! thanks!

[Altera_Forum]

You use reset = 1 when the reset signal is active low (reset_n). If you have an active low reset and you hardcode it low then you'll get stuck in reset.

[Altera_Forum]

Yes but my system reset is active high.

[Altera_Forum]

--- Quote Start ---  You should read more about Avalon Interface Spec.  --- Quote End ---    Hi, thanks! Yeah but the spec is long. Maybe if possible, could you please tell me which section? Because I am running out of time. I need to get this done by this week. Thanks!

[Altera_Forum]

if you have a Fifo, you should not connect chipselect and write/read signals to your adder. Rather you connect them to your incoming/outgoing fifo, as that is where you write/read the data.  

Actually, the fifos should decouple the adder completely from the avalon interface. The write and chipselect lines to your adder should be fed by an internal logic, which is not too difficult: write could be just clock, while chipselect is (fifo_in_not_empty and fifo_out_not_full). So your adder works with the data as long as your fifos allow.

[Altera_Forum]

Hi. does it mean that for my adder, i dont have to put clock, reset and chipselect signals? Then for the write signal at adder, i connect it to clock. however for the address at adder, '0' means write the data in to be calculated and '1' means read the result to readdata to display the output. where should i connect it? thanks!

[Altera_Forum]

besides, is it possible for FIFO to write and read at the same time?

[Altera_Forum]

You certainly need a reset, to have a clear start condition. 

You certainly need some clock, or nothing will work. As said above, the chipselect I would connect to fifo_in_not_empty <AND> fifo_out_not_full, so your adder stops when the fifos are empty/full. The write signal for your adder is the same as the read signal for incoming fifo (as the date read from it shall be written to the adder). Does you adder give a signal when it's done processing? That should go then to outgoing_fifo write signal.   Use the address signals for the incoming fifo write and outgoing fifo read. You'll need to <AND> it with the avalon write signal, so you don't write data into the incoming fifo when accidentally reading from address 0. (Same goes for outgoing fifo.)

[Altera_Forum]

--- Quote Start ---  Does you adder give a signal when it's done processing? That should go then to outgoing_fifo write signal.   --- Quote End ---    No, once it adds the two number, i will wait for address = '1', then it will send the result out.    --- Quote Start ---   Use the address signals for the incoming fifo write and outgoing fifo read. You'll need to <AND> it with the avalon write signal, so you don't write data into the incoming fifo when accidentally reading from address 0. (Same goes for outgoing fifo.)  --- Quote End ---     this part is a bit confusing. the avalon write signal is the external signal? when address = 0, the data will be written into adder, when address = 1, the result will be sent out from adder.  besides, can FIFO write and read at the same, which means, wrreq and rdreq both is high at the same time?

[Altera_Forum]

yes. the M9K blocks are dual-interface ram blocks, that can be read and written at the same time. 

 the avalon has a write and a read signal. How else could you determine, whether to write to or read from the specified address? The address lines are there to select, which register (in your case fifo) to read from or write to.  For the fifo design, theres no need for the adder to wait for anything. It could just output the write signal to the fifo, and all is good.

[Altera_Forum]

OK. i am trying now and will post the result.

[Altera_Forum]

hi... i have done doing the block... i can get the result now and the result is correct... but the time it fetch the result is different... pls see the attachment.. 

 p/s: as for now, i didnt use address for adder anymore. once chipselect is high, it will fetch data into the adder, calculate it and fetch the result to the output at the same time.

[Altera_Forum]

Why did you connect the avalon read signal to the incoming fifo? 

The avalon reads data from the outgoing, does it? The read signal from the incoming fifo should come from the adder, as this one reads data from the fifo, or does it? The readrq for the incoming fifo and the write signal for the adder should come from chipselect&clk.  I like the trick with the read/write enables for the fifo.  Of course the data needs some clock cycles to move through the fifo...

[Altera_Forum]

Yeah, i did edit the signal... the result still the same... does it consider as correct for the result?  

 hahaha. i dont know how to connect the signal to interrupt, so i just use tristate buffer.  in the attachment, the picture (block.jpg) is the overall block. now i have the block, how to connect that block with DMA?

[Altera_Forum]

You're using SOPC-Builder, do you? 

A DMA is just 2 Avalon masters, one for reading and one for writing. You want to transmit data from where to where?

[Altera_Forum]

Yes, SOPC. I want to transfer from SDRAM to this block then from this block to SDRAM back. 

 Update: I tried to run it in Nios II IDE, but the result i got were wrong...  correct result: 0, 2, 4, 6, 8....298 result obtained: 294, 296, 0, 2, 4...292  i am adding number 0 till 149... suppose 294 = 147+147   is it because of the delay in fetching the result previously? if yes, how to solve it? thanks!

[Altera_Forum]

How much data have you fed it? 

How high is the fifo fill count (usedw)? Might it already have wrapped around somehow, and read old values from a previous run? Have you tried to feed it different values?

[Altera_Forum]

yes, the data was due to previous run. initial run (1st time), the initial result is 0,0,200, 0,2,4,6.... second run, the result was as in above. is it due to the block is running under same clock? 1st positive edge of the clk, 2nd read the data, 3rd data go into adder, 4th data go into fifo_out, 5th, data go out to be displayed as result.

[Altera_Forum]

yes, exactly. 

When you read from an empty fifo, the result is not really predictable. That's why one would check before, how many values are stored in it, and maybe erase old contents.  Using an address decoder, you can trigger different actions (like, erase all fifos, set a halt condition on the adder, read the usedw value instead of a result,...).  That's what creates the register representation in a periphereal.  Have you had a look at the avalon master PIO example? That shows quite a lot of this concept.

[Altera_Forum]

I see. No, I dont have the example. Is it that I have to re-do?

[Altera_Forum]

it's an enhancement. you decide if you need it, or if you can live with what you got..

[Altera_Forum]

I have no idea what you're trying to do here... 

   1. PIO -> Avalon-MM 2. DMA -> Avalon-MM 3. SGDMA -> Avalon-ST   Look at this http://www.johnloomis.org/niosii/pio/pio_example1.html   This is a easy way to check your data with your logic design work or not in hardware real-time...