Uart data ready

[Altera_Forum]

Hi all, 

 I am periodically sending data from LabView to my cycloneIII development kit (bemicro) and I want to check if there is data available to be read in NIOS II. Unfortunately, I have not been able to use the data ready bits, can someone enlighten me on how to do this?!  Do I need to use  ALT_UART_READ_RDY 0x1 or ALTERA_AVALON_UART_CONTROL_RRDY_MSK (0x80) ?  If yes, how am I supposed to do so? Any help would be appreciated! marek

[Altera_Forum]

To test if there is data ready to be read I use the following code. 

   status = IORD_ALTERA_AVALON_UART_STATUS(UART_BASE);  if (status & ALTERA_AVALON_UART_CONTROL_RRDY_MSK)  {  }  However, it seems that the if statement is false even when there is data available. Can anyone help?

[Altera_Forum]

--- Quote Start ---  status = IORD_ALTERA_AVALON_UART_STATUS(UART_BASE); if (status & ALTERA_AVALON_UART_CONTROL_RRDY_MSK) { }  --- Quote End ---    In this IF statement,you have put ' & ' operator which is not logical and.It is bitwise and,so any value except 0x00,will cause to go into IF body  I think you should compare your IF result to some specific hex value that you want to get  Ex: if ( status & ALTERA_AVALON_UART_CONTROL_RRDY_MSK == 0x..)  {  temp_read= read_data;  }

[Altera_Forum]

No, if (status & altera_avalon_uart_control_rrdy_msk) is a good code (fails only if mask=0x0 which doesn't usually happen).

[Altera_Forum]

Thanks for the replies. Unfortunately I still didn't get the code to work, the if statement returns remains false... Does anyone have any suggestions? 

 BTW, it should read: if (status & altera_avalon_uart_status_rrdy_msk) instead ofif (status & altera_avalon_uart_control_rrdy_msk).

[Altera_Forum]

Hi again, 

 It seems that the foloowing statement does not return the proper status bits.  status = IORD_ALTERA_AVALON_UART_STATUS(UART_BASE);  Are there any specific functions that can mess with the status bits? Do I need to initialize something in particular for this to work? Any special includes?  I would appreciate some help!!!

[Altera_Forum]

Be sure that uart_base matches to your SOPC UART_BASE :  

maybe you have changed your sopc (in Quartus SOPC Builder) and you have forgotten to rebuild your "system library" (I don't know the exact name in NIOS > 9.1, perhaps "BSP" :confused:) in NIOS IDE (or SBT or ...)

[Altera_Forum]

Thanks for the reply mmTsuchi. 

 The UART_BASE matches the SOPC UART_BASE and the BSP is up to date. I can send data (TRDY behaves as expected) but RRDY still remains low even when data is sent (I checked the data is actually sent, I can even read it in the NIOS, but RRDY remains low).  I seem to observe that RRDY goes high for a very short amount of time, like a glitch and returns to zero even when the data is not read from the tx.  Any ideas? Anyone?

[Altera_Forum]

hi, I should read "and returns to zero even when the data is not read from the rx", shouldn't I? ;-) 

 Are you sure there is no other iord_altera_avalon_uart_rxdata(uart_base) in your NIOS prgoram.  Are you sure about your serial protocol ? câble (cross-câble ?) and config ( for example 38400-8-n-1)  Are you sure that your Labview doesn't send continuously data ? (You can check Uart ROE bit status) You can send data from an other computer with hyperterminal (does not exist in Windows 7 ! :-D :-D :-D) instead of LabView. 

[Altera_Forum]

Hi, Yes, rx and not tx ;-) 

Yes, I am sure the NIOS doesn't contain any other iord_altera_avalon_uart_rxdata(uart_base)...  Labview sends the data through USB onto the BeMicro development board (containing a Cyclone III) and the data is sent when the user pushes a button, thus there is no continuos data stream.   I've read in the forum about issues with the interrupts and/or HAL drivers that could interfere with the STATUS bits, do you think there is potentially something along that line?   BTW, I'm using a mac with parallel desktop to run labview, nios & quartus, do you think that could be an issue? Unfortunately I don't have a pure windows machine with the proper software to test it...  Cheers, Marek 

[Altera_Forum]

By the way, here's the code I currently use for debugging. Id basically reads the STATUS bits and sends them to labview. It reads 64 continuosly, even if labview is writing onto rx... 

 # include <stdio.h># include <string.h># include "alt_types.h"# include "altera_avalon_spi.h"# include <altera_avalon_spi_regs.h># include "altera_avalon_uart.h"# include "altera_avalon_uart_regs.h" // these includes allow us to perform a quick sanity check that the system was properly assembled in SOPC Builder# include "system.h"# include "inc/system_validation.h"# include <stddef.h> // all helper routine includes are condensed into this one file for neatness# include "inc/main_includes.h"# include "sys/alt_irq.h"  alt_u16 status = 0;  int main(void) {   alt_u16 new_divisor; //clk speed divisor to uart speed  alt_u32 serial_speed = 1000000; //uart speed, as to be match with labview VI. max 1250000  alt_u32 FPGA_CLK = 50000000; //set at 50Mhz in Quartus  uart_init(); // see src/uart_util.c  new_divisor = (alt_u16)(FPGA_CLK/serial_speed+0.5); //set the divisor for the uart speed wanted  IOWR_ALTERA_AVALON_UART_DIVISOR(UART_BASE, new_divisor);  validate_me();    while(1) //loop for the run||  {    if (IORD_ALTERA_AVALON_UART_STATUS(UART_BASE) & ALTERA_AVALON_UART_STATUS_TRDY_MSK)  {  status = IORD_ALTERA_AVALON_UART_STATUS(UART_BASE);  IOWR(UART_BASE,0x01, status);  } }

[Altera_Forum]

On more thing, I added the following line to intialize the CONTROL register. The problem is still the same though... 

 IOWR_ALTERA_AVALON_UART_CONTROL(UART_BASE, 0);

[Altera_Forum]

Ah aH :-) 

(You can enclose your code with ... )  Try if (IORD_ALTERA_AVALON_UART_STATUS(UART_BASE) & ALTERA_AVALON_UART_STATUS_RRDY_MSK) // be coherent { status = IORD_ALTERA_AVALON_UART_STATUS(UART_BASE); // status=64 means "TRDY=1" and that is normal. // IOWR(UART_BASE,0x01, status); IOWR_ALTERA_AVALON_UART_TXDATA(UART_BASE,status); // status is 16-bit wide , OK }  For reference , http://www.altera.com/literature/ug/ug_embedded_ip.pdf (UART CORE REGISTER MAP en page 79)  I may laugh if since the beginning, your are looking for the wrong register bit : trdy instead of rrdy :-d My teacher would says "Fatal Error" and give 0 point to the whole exam ! :-)   On an other side, # include "system.h" // doesn't mean that system.h matches to SOPC, even if system.h exists and makes no software build error. You could have an working system.h but very old and not matching.

[Altera_Forum]

Hey, 

 Yes, I should have explained what I'm trying to do. This was for debugging purposes, I write the status to the UART to visualize it on the PC and see if the RRDY bit ever goes high when sending data.   The if statement was just added because the NIOS was firing too quickly, thus the status is written to the uart when transmit is ready.   The problem remains the same, RRDY never goes high even though data is sent through the UART...

[Altera_Forum]

System.h is up to date, I regenerated the SOPC, compiles the quartus project and regenerated the BSP. 

 It remains that I continuosly read status=64 (TRDY high) when I expect 128 (or more, RRDY high) indicating that there is data ready to be read on the UART...

[Altera_Forum]

--- Quote Start ---  When a new character is fully received via the RXD input, it is transferred into the rxdata register, and the status register's rrdy bit is set to 1  --- Quote End ---   Are you sure that data come from Labview to your UART ? cable problem ? Did you spy the RX-line of your UART ? See something (use a scope) To be continued :-)

[Altera_Forum]

Ok. The code is finally working! The read ready interrupt (in the control register) must be disabled first, otherwise the RRDY mask does not display the proper value. I used the following command to disable the interrupt: 

IOWR_ALTERA_AVALON_UART_CONTROL(UART_BASE, 0);