Ultimate OSS 2x GBIT NIC on Linux by PHY to FPGA on Cyclone V SoC DP0-Nano GPIO trd!

[Altera_Forum]

Hi, 

  I want to plug in two gigabit ethenet transcievers to my DP0-Nano CYclone V SoC.   The way to do this must be the GPIO:s. By this thread, I wish to clarify how to do this, preferably all the way up to that Linux or FreeBSD would accept the two ethernet devices, and recognize them as Realtek or Intel gigabit.  I would very much appreciate if I could use the ordinary Realtek/Intel gigabit NIC drivers, with DMA and all, for the OSS-FPGA-implemented NIC.   So, the actual NIC:s are implemented by the FPGA.    The purpose is a filtering bridge/firewall.     question 1: Does anyone sell a Gigabit RJ45 transciever to 2x10 GPIO pins connector today?     question 2: What does the PIN mapping need to be from for instance the Marvell 88E1510 Gigabit Ethernet PHY [1] to the GPIO? Does any particular consideration needs to be given to interrupt handling?     question 3: What would be a suitable open-source gigabit ethernet controller implementation to run in the FPGA?     question 4: What are the commands to set up the ethernet in the FPGA from Linux or FreeBSD?     question 5: How will Linux/FreeBSD interface the NIC:s in the easiest way? How is that set up?     question 6: Would it be relevant that the FPGA somehow would implement a (virtual) PCI-express bus, just so that Linux/FreeBSD drivers would have an easier time interfacing the FPGA-based NIC?     Thanks! Tinker     [1] Used on the http://ethernetfmc.com/documentation/ card. Docs: http://www.marvell.com/transceivers/assets/marvell_alaska_88e1510_18-002_product_brief.pdf

[Altera_Forum]

I think you'll struggle to run 2 Gigabit Ethernet controllers, reliably, through the GPIO on the DE0-Nano-SoC Kit. No, I'm not aware of any modules that will simply plug onto the GPIO exposed. 

 I suggest, to aid your initial understanding of how the Phy should be connected up, you consider looking at the documentation for a dev board that already has two connected up. The cyclone v e fpga development kit (https://www.altera.com/products/boards_and_kits/dev-kits/altera/kit-cyclone-v-e.html) has two Marvell Gigabit Phys. They'll connect up exactly as you need. Look through the documentation, including the schematic. You can download all this via the links at the bottom of the page.  Also look at the cyclone v soc development kit (https://www.altera.com/products/boards_and_kits/dev-kits/altera/kit-cyclone-v-soc.html). Perhaps this is more representative of the SoC solution you want. However, the dual Phys on this are only 100Mb.  I hope this helps guide you, in the first instance, to a suitable hardware solution.  Cheers, Alex