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Unconstrained inputs/outputs

Altera_Forum
Honored Contributor II
‎02-25-2011 02:23 PM
1,501 Views

Hi, 

 

I just started to use the TimeQuest Timing Analyzer to constraint a new VHDL design (EP3C16). I managed to constraint my clock and derived clocks. 

 

I have a process which is a state machine, where the states are changing based on some asynchronous IOs. 

 

When I compile my project, I end-up with 'Unconstrained Input/Output Ports'. I went through the tutorials and am still confused on how to constrained those. 

 

Let's say I have a state where I am waiting for an IO to go high to change to the next one (synchronous on the master clock). This input is coming from an external device Gumstix computer.  

 

How should I constraint that input port? 

 

Thank you for your help. 

 

Mathieu
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Altera_Forum
Honored Contributor II
‎02-25-2011 03:01 PM
518 Views

Have you read also the TQ user guide written by Rysc? 

http://alterawiki.com/wiki/timequest_user_guide 

I think what you need is explained very clearly here.
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