Hi,I have a code which I am using in Qsys. The ports are reported in unconstrained paths in Timequest. What is the best way to eliminate them? I have a clean timing before constraining these ports(input/output). When I try to set input or output delay, then I get a setup violation of around -6.
You need first correct constraints then pass timing. There is no point passing timing when constraints don't exist or are wrong (that will be false pass).io timing is your domain of design and depends on board delays of clock and data and the way it is sampled in or out. if such ports are irrelevant you can relax the constraints on them.
Hi Kaz,I have tried doing them. When I have a constraint on (output ports) output delay min and max of 0, I have a negative slack of -1.5. Is there any option how can I correct the same?
You should not set output delays to 0. You need a range of delay (that's why it's called min and max) that defines the external delays to meet setup and hold timing at the output ("downstream") device. Check out this online training to learn how to calculate the values for set_output_delay:https://www.altera.com/support/training/course/odsw1118.html