Unexpected result after simulation of Avalon Edge Detector example in DSP Builder

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

Unexpected result after simulation of Avalon Edge Detector example in DSP Builder

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I've been checking Avalon Edge detector in DSP Builder (versions 7.2 and 8.0) and the image result of the simulation shown is 10 pixels moved to the right.

Any suggestion about this harmful effect?

Any suggestion in order to avoid it?

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