Greetings. I am doing board bring-up on a new design that uses a Cyclone 10GX (PN: 10CX105YF672E5G). When I execute a AutoDetect in the Quartus Pro programmer it reports UNKNOWN_2E720DD. The C10GX handbook chapter9 page 240 shows that 02E20DD is the correct IDCODE for the GX105. I ran the JTAG Chain Debugger IDCODE Iteration Test several hundred iterations and it reported that "JTAG chain connection is good and consistent". I was using Quartus Pro 17.1 and updated to 18.0 and get the same unknown ID.
I made a simple project that passed a clock signal to an output test point. The sof loaded ok through the JTAG (programmer GUI reported success), CONFIG_DONE went high (always a good thing), and my clock showed up at the test point. So the board is behaving at some basic level. I added a NIOS processor and had it toggle an output pin in a forever loop. However I could not connect through the Eclipse NIOS debugger nor the System Console (System Console reports 02E720DD@1 connected to the USB-BlasterII). I added Signal Tap to the project but it reports device "@1: (0x02E720DD)" when I execute the Scan Chain button. It seems that Quartus just does not recognize the ID which looks correct. Does anyone have a suggestion how this can be overridden? Or is the problem really on my end? Thanks, BillLink Copied
Hi,
1.To read the device IDCODE correctly, you must issue the IDCODE JTAG instruction only when the nCONFIG and nSTATUS signals are high. 2.To remedy this problem, perform the following in the Quartus® II Programming window:Thanks for your reply Anand!
I need a bit more help. I verified the nCONFIG and nSTATUS lines are high. I can get to the "Edit Device" window ok, but I'm stuck trying to find the instruction register length for the Cyclone 10 GX. Chapter 9 of the handbook points me to this URL for BDSL files but Cyclone 10GX devices are not in the list: https://www.altera.com/support/support-resources/download/board-layout-test/bsdl/_11491/bsd-11491.ht... Is there another place I should be looking for the instruction register length?Hi,
For BSDL files for Cyclone 10GX devices and more information check below link. https://www.altera.com/support/support-resources/download/board-layout-test/bsdl/cyclone-10-gx.html https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/an/an039.pdf The Instruction Register (IR) length for all Altera® FPGAs and CPLDs will be 10 bits long. Let me know if this has helped resolve the issue you are facing or if you need any further assistance. Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation)Anand,
We were going down the wrong path. I found another post that suggested this is an issue with the JTAGserver not finding the correct files and recommended removing and re-installing Quartus. I did this and now the programmer, SignalTap, and NIOS debugger report "10CX105Y" correctly. Problem solved. Thanks, BillFor more complete information about compiler optimizations, see our Optimization Notice.