Ununderstood error message

Altera_Forum · ‎07-15-2009

Hello,

I am working on a VHDL project using the Altera DK-N2EVAL-3C25N development kit which is a NIOS II CYCLONE III environment.

While proceeding with the "Start Analysis & Elaboration" menu, I have encountered this error message: 'error (10482): vhdl error at audio_project.vhd(40): object "sclk" is used but not declared'.

Knowing that i have already declared "SCLK" in the proper place,I am still wondering where the problem is.

This is the code portion where this signal is declared:


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use work.audio_config.all;
entity audio_project is 
port( 
reset: in std_logic;
ADCDAT : in std_logic_vector(7 downto 0);
DACDAT: out std_logic_vector (7 downto 0);                              
BCLK : in std_logic
);
end audio_project;
architecture structural of audio_project is
component fsm is 
port( 
reset: in std_logic;
BCLK : in std_logic;
SCLK : inout std_logic;
SDIN: inout std_logic
);
end component fsm;
component FIFOMXN is
generic( n : Positive := 8;
         m : Positive := 48
); --m is fifo depth, n is fifo width
port(reset, WRREQ, RDREQ, BCLK : in Std_logic;
DATAIN : in Std_logic_vector((n-1) downto 0);
DATAOUT : out Std_logic_vector((n-1) downto 0);
FULL, EMPTY : inout Std_logic);
end component FIFOMXN;
begin
C1 : fsm port map ( 
reset => reset,
BCLK=>BCLK,
SCLK=>SCLK,
SDIN=>SDIN
);
fifo_recep: FIFOMXN port map( reset, WRREQ, RDREQ, BCLK, ADCDAT, DATAOUT, FULL, EMPTY);
fifo_trans: FIFOMXN port map( reset, WRREQ, RDREQ, BCLK,DATAIN,DACDAT, FULL, EMPTY);
end structural;

Altera_Forum · ‎07-15-2009

Hi alaaayed:

the port or signal SCLK is not declared in your design. The SCLK that you describe from the fsm module is the name of the port internal in the module but is not known in audio_project.

To solve the problem, you should add the definition of the SCLK signal.