Unused IO Banks

[Altera_Forum]

If im not using any pins on a IO Bank do i need to connect up its IO VCC? or can i leave this bank completely un powered? 

 Regards Russell Pirie

[Altera_Forum]

--- Quote Start ---  If im not using any pins on a IO Bank do i need to connect up its IO VCC? or can i leave this bank completely un powered?   --- Quote End ---    Which device are you using?  FPGAs have a power-on-reset that will not release until the power rails are all within tolerance.  I'm not sure what flexibility there is in not having some VCCIO banks power up.  If you read the handbook and cannot quite figure it out, you could always start removing power from VCCIO banks on a development board and see if the FPGA still works. Eg., the Terasic DE-115 has VCCIO jumpers on some of its banks, while other boards have resistors between their main power rails and the VCCIO banks.  Cheers, Dave

[Altera_Forum]

im using the EP1C3T100C8N, but only actually using 14 IO pins so two banks are unused 

 I think i will power the other two banks any way, im not saving any thing by not powering them just a little bit extra routing lol  thanks for your reply :)

[Altera_Forum]

--- Quote Start ---  im using the EP1C3T100C8N, but only actually using 14 IO pins so two banks are unused   --- Quote End ---    p253 has the statement I recall:  http://www.altera.com/literature/hb/cyc/cyc_c5v1.pdf  "Normal operation does not occur until both power supplies are in their recommended operating range"    --- Quote Start ---   I think i will power the other two banks any way, im not saving any thing by not powering them just a little bit extra routing lol   --- Quote End ---    That would be my advice.  Cheers, Dave

[Altera_Forum]

Thanks for your help :)

[Altera_Forum]

You're welcome. 

 Another word of advice - make sure to connect the JTAG signals!  Cheers, Dave

[Altera_Forum]

im going to be programming the fpga using a micro controller when the board boots up, so no need for JTAG. although would you recommend having a header any way just incase? 

 can you have a fpga hooked upto a JTAG header and connected to a micro controller(for loading the bit file) at the same time?  Im very new to FPGAs     im currently using 'PS Configuration Circuit with a Microprocessor' from the doc 'AN 250: Configuring Cyclone FPGAs'  but it would be nice to add a JTAG header to that system as well so i can quickly test new designs, and only use the boot off the micro controller once im happy and the board works standalone  can the two be combined? i had a quick read of the AN 250 doc but could not find any examples of boot from micro controller combined with JTAG or AS header :(

[Altera_Forum]

--- Quote Start ---  but it would be nice to add a JTAG header to that system as well so i can quickly test new designs, and only use the boot off the micro controller once im happy and the board works standalone  --- Quote End ---    Yes, so you have already answered the question yourself.    --- Quote Start ---  can the two be combined? i had a quick read of the AN 250 doc but could not find any examples of boot from micro controller combined with JTAG or AS header  --- Quote End ---   JTAG configuration and debugging functions are available in any configuration mode. AS mode is alternative to PS. You need switches or jumpers for MSEL to select between both.

[Altera_Forum]

Im with you. 

 Thanks :)

[Altera_Forum]

--- Quote Start ---  im going to be programming the fpga using a micro controller when the board boots up, so no need for JTAG. although would you recommend having a header any way just incase?   --- Quote End ---  The JTAG interface is;  1) A programmer 2) A communications interface 3) A logic analyzer interface 4) A NIOS processor debugger interface 5) A custom JTAG interface  .... and many more  The passive serial interface is *only* a programmer interface. You need it to program you device at power on. The JTAG interface is for all the problems you haven't thought of yet :)  Cheers, Dave

[Altera_Forum]

I have added it hehe :) 

 If you dont mind could you have a quick look at my schematic and see if i have made any simple mistakes / missing any thing.  The design is a basic LPC2103 micro controller that configures the FPGA in PS mode at boot. The LPC2103 also has a simple 8bit bus to the FPGA to send it bytes of data.  the FPGA just has 6 outputs to a simple pcb header   very simple design hehe :)

[Altera_Forum]

--- Quote Start ---   If you dont mind could you have a quick look at my schematic and see if i have made any simple mistakes / missing any thing.   --- Quote End ---    You have 3.3V/800mA generated from 12V. If you really expect this supply to generate 800mA, it will dissipate P = (12V-3.3V) x 0.8 = 6.96W. It'll get way too hot. Use a switch-mode supply if you really expect to use this much power. A similar argument holds for the 5V supply.  I personally prefer to buffer or put series resistances in the path between the JTAG header and the JTAG pins on the FPGA. This provides some ESD protection ... that zap you hear, right before your board stops working.  nCONFIG needs a pull-up or pull-down. The low-to-high transition on that signal is what resets the FPGA. See this doc for more details:  http://www.ovro.caltech.edu/~dwh/carma_board/fpga_configuration.pdf  Put a series resistor in your DCLK path and on your oscillator output (to control ringing).  Where are all your decoupling capacitors? Make sure you have one per power pin for every device.  Check your crystal oscillator circuit. It seems a bit simple. I thought they normally had low valued capacitance near them to tune the oscillation.  Cheers, Dave

[Altera_Forum]

--- Quote Start ---  You have 3.3V/800mA generated from 12V. If you really expect this supply to generate 800mA, it will dissipate P = (12V-3.3V) x 0.8 = 6.96W. It'll get way too hot. Use a switch-mode supply if you really expect to use this much power. A similar argument holds for the 5V supply.  --- Quote End ---    I dont need 800ma i dont think the circuit will draw any where near that. im guessing only 100 or so?, i just like the lm1117 range of regulators + have tapes of them so decided to use it.    --- Quote Start ---  I personally prefer to buffer or put series resistances in the path between the JTAG header and the JTAG pins on the FPGA. This provides some ESD protection ... that zap you hear, right before your board stops working.  --- Quote End ---    sounds good, what value resistor are you thinking some thing like a 1k?    --- Quote Start ---  Check your crystal oscillator circuit. It seems a bit simple. I thought they normally had low valued capacitance near them to tune the oscillation.  --- Quote End ---    im not 100% sure on this i was just copying a simular schematic, ill look at the oscillator part data sheet and see if it needs this cap. :)    --- Quote Start ---  nCONFIG needs a pull-up or pull-down. The low-to-high transition on that signal is what resets the FPGA. See this doc for more details:  --- Quote End ---    ah cool i shall add this.    --- Quote Start ---  Where are all your decoupling capacitors? Make sure you have one per power pin for every device.  --- Quote End ---    all my decoupling caps are under the regulators top right of my schematic, i have 1 cap per pin for the 1.5core voltage and 2 caps, i think i just need 2 caps for my io banks as im only using 2 banks and these banks only use 3 pins and 2 of the pins are very close together. so i think i can get away with just 2 decoupling caps?    --- Quote Start ---  Put a series resistor in your DCLK path and on your oscillator output (to control ringing).  --- Quote End ---    will do, what values should i be using?      thanks for all your feed back its VERY useful :) and ill make all your amendments.

[Altera_Forum]

ESD resistor: 100-Ohms is fine, 1K is Ok if thats what you have. You can always change them later if there is a problem with voltage drop. 

 Series resistors: something around 30-Ohms is good. Whatever you have close is good enough (eg., as big as 100-ohms would probably be ok - the key is to have them on the PCB ).  Cheers, Dave

[Altera_Forum]

i can use any value, ill use your suggested values :) 

 OMG i completely forgot my data clock from the lpc to the fpga to clock the byte in haha, that would of sucked!!! lol