Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
21593 Discussions

Unused bank - VCCPD, VCCIO and VREF pins

Altera_Forum
Honored Contributor II
3,024 Views

Hello everyone, 

 

If I do not want to use a certain bank of the Cyclone V, do I have to power the VCCPD, VCCIO and VREF pins? 

 

Cheers, 

Adam
0 Kudos
5 Replies
Altera_Forum
Honored Contributor II
1,987 Views

Hi, 

 

I want to ask same question. I have Cyclone V device and don't want to use a bank. Should I power that bank?
0 Kudos
Altera_Forum
Honored Contributor II
1,987 Views

The handbook (Table 10-2) says that the POR circuit does not monitor VCCIO but it does monitor VCCPD. From that I'm guessing you have to power both VCCIO and VCCPD in all banks. No problem not powering VREF for sure. 

 

What is your motivation for not powering the bank? The power savings would be minuscule in an idle bank.
0 Kudos
Altera_Forum
Honored Contributor II
1,987 Views

Hi Adam, 

 

Generally we could refer to the CV pin connection guidelines (https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/dp/cyclone-v/pcg-01014.pdf) to see how to deal with the unused pins. In CV pin connection guidelines, it says unused Vref pin can be connected to VCCIO of its bank or GND. As for VCCIO and VCCPD, there is no mention about unused pin connection. Thus, I believe VCCIO and VCCPD should always be powered even the bank is unused.
0 Kudos
Altera_Forum
Honored Contributor II
1,987 Views

Keep the power rail connected even if you are not using it. Not much power consumption. If for some reasons you cannot connect a rail to it, at least keep those POR monitored supplies connected.

0 Kudos
Altera_Forum
Honored Contributor II
1,987 Views

Yes, I agreed with nicejob comments. There is minimal power savings when powering down the VCCIO voltages. Here is the solution posted by Altera can be your references: 

https://www.altera.com/support/support-resources/knowledge-base/solutions/rd12172008_333.html
0 Kudos
Reply