Use PLL between the dedicated clock input pin and output pin.

[Altera_Forum]

I am using the cyclone II series, and my global clock(32M,input_clk) is inputed by a dedicated clock input pin(clk0).  

 Now I need a clock which is 4MHz divided by input_clk, and output it to a dedicated clock output pin(PLL1_out)。  What can I do? I try to use a PLL, but it doesn't work, said:"Post divider max count exceeded".   Any advice? Thank you!

[Altera_Forum]

Right out of my head the slowest clock a cyclone II pll can generate is ~12MHz 

 plls in cyclone ii devices (http://www.altera.com/literature/hb/cyc2/cyc2_cii51007.pdf)

[Altera_Forum]

The restriction is in the VCO frequency range and maximum divider count of 32. You have to use a post divider in logic. If a specific output timing is required for the output, you can supply the post divider with a phase shifted clock and adjust for the extra delay. The slightly increased jitter and timing inaccuracy shouldn't matter that much at 4 MHz.

[Altera_Forum]

--- Quote Start ---  The restriction is in the VCO frequency range and maximum divider count of 32. You have to use a post divider in logic. If a specific output timing is required for the output, you can supply the post divider with a phase shifted clock and adjust for the extra delay. The slightly increased jitter and timing inaccuracy shouldn't matter that much at 4 MHz.  --- Quote End ---    I forgot to mention that I use the LVDS I/O standand on both the input clock and output clock. When I put a divider between the PLL and output pin, an error happened: Pin "clkout" with LVDS I/O standard must be driven by the external clock output of an enhanced PLL".   What's the solution? I totally have no idea.

[Altera_Forum]

It's easy in this case, because Cyclone II has no real LVDS driver. You must use a resistor network at the output to achieve a correct LVDS level anyway. For a slow 4 MHz output, it's no problem to use a pseudo-differential output by connecting an inverter for the inverted pin. This is the only way to get a differential output at the dedicated clock output pins without driving it from the PLL.

[Altera_Forum]

--- Quote Start ---  It's easy in this case, because Cyclone II has no real LVDS driver. You must use a resistor network at the output to achieve a correct LVDS level anyway. For a slow 4 MHz output, it's no problem to use a pseudo-differential output by connecting an inverter for the inverted pin. This is the only way to get a differential output at the dedicated clock output pins without driving it from the PLL.  --- Quote End ---    To FvM: Actually,I don't need a LVDS clock output, but my input clock already use the LVDS standand, and the output pin was assigned in the same I/O bank, so I have to set the output pin with LVDS standand.  In this situation, what can I do?

[Altera_Forum]

--- Quote Start ---  so I have to set the output pin with LVDS standand  --- Quote End ---  Generally, not. You have to use the same I/O voltage and you have to keep some distance rules, but you can use different I/O standards in a bank.

[Altera_Forum]

O, thank you, FvM. 

I set the output pin to 2.5V independantly, and it worked.