Use conf.done pin

[Altera_Forum]

I am using a Cyclone-IV device which is configured as a combination of a NIOS-II and other logic units. 

 "NIOS II reset" is an input signal to reset the NIOS-II processor inside the FPGA. In addition to the NIOS-II, the other internal logic units need reset signals as well.   My question is "can I use the conf.done signal (pin) to reset the NIOS-II and the internal logic units?" I don't think that the conf.done is affected by doing this. However, in this way, the conf.done pin has to be assigned in the Pin Planner or the assignment editor but this pin is greyed out. It seems to me that doing this is perfectly fine but I don't know why it is not allowed. Many thanks for comments and suggestions.

[Altera_Forum]

I don't think it is possible to use CONF_DONE as a reset, because the usermode is entered after CONF_DONE is released. So when entering the useremode, this signal is High per definition (if pulled up, it is open collector). See fig 8-16 and table 8-10 of the Cyclone IV handbook. 

 Maybe you can feed this signal through a delay circuit on your PCB and use the output of this circuit as a reset-signal for your logic.  Good luck, Ton

[Altera_Forum]

What I usually do is run the optional INIT_DONE line through an external reset generator to generate the reset signal for my logic. 

 However, you can and should also have an internal reset generator circuit for your logic. Here are some threads to look at: http://www.alteraforum.com/forum/showthread.php?t=6602&referrerid=2226 http://www.alteraforum.com/forum/showthread.php?t=6621&referrerid=2226  Jake

[Altera_Forum]

Hi Jake, 

 When you take the signal from the optional INIT_DONE line to your external reset generator, you still need a input pin to input your reset signal from your external reset generator to the FPGA in order to reset your NIOS-II and internal logic units. Is that correct?   Many thanks,   Bcao

[Altera_Forum]

Yes. correct. I don't know of any way to internally read the CONF_DONE or INIT_DONE lines. If doesn't really make sense you see. If your FPGA is up and running, then obviously you are configured and initialized. So normally we use an internal reset generator circuit that becomes active after initialization to reset internal logic (like the NIOS). 

 Jake