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I have a signal consisting of very fast sub-nanosecond pulses from the output of a comparator, and I am wondering if it's possible to use the multi-gigabit transceivers to sample and acquire the signal into the FPGA.
The pulses are derived from a random physical process, so they are completely asynchronous and have no intrinsic clock rate associated, and the signal is also not DC-balanced, therefore it also needs to be DC-coupled into the receiver inputs. For the time being I will assume we can successfully translate the comparator's logic levels to meet the receiver's differential and common mode voltage requirements.
My question is whether the transceivers can be set up to sample at a fixed frequency. I understand that CDR circuit can be operated in manual mode, and that there is a signal "locktoref". However it is not clear from the manuals whether my intended usage is sanctioned or if it produces well defined behavior. Can the receiver be continuously operated in locked to reference mode in order to sample a totally asynchronous signal? I would like to set up the PLL such that the receiver samples continuously at 10 GHz.
In essence, the receiver would be operating as a 1-bit ADC sampling the output signal from my comparator at a fixed frequency. I also wonder whether any metastability due to sampling near the edge of the pulse will be resolved once the deserialized signal is provided to the FPGA fabric, or if metastibility will cause any issues internal to the transceiver circuit.
I have already determined competitor A's transceiver can be operated in this mode, however the cyclone 10 GX has a better total # of transceivers in the price range we are targeting.
Thanks
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Hi,
As I understand it, you have some inquiries related to our C10GX RX CDR in lock-to-ref mode. For your information, when the CDR is manually forced to lock-to-ref mode, the CDR is not tracking the incoming data. We cannot guarantee if the data will still be sampled correctly. As I understand it, I have come across cases where the incoming data rate is lower than the supported range of CDR, the application will put CDR to lock-to-ref mode and recover the data using custom logic.
Therefore, specific to your target implementation, I am not sure if the CDR is able to sample the data correctly since the CDR is not intended to sample data at lock-to-ref mode. If you have a C10GX hardware available, you might want to perform some tests to check out if your target implementation could work. Sorry for the inconvenience.
Please let me know if there is any concern. Thank you.
Best regards,
Chee Pin
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Thanks for your response.
Basically it is not serial digital data, that is the reason for my question. It is not the common usage of transmitting/receiving serial data.
It is a totally asynchronous stream of pulses, not synchronous to any clock. So I do not want to lock the CDR to the data... I just need to disable CDR completely and over-sample the input continuously at 10 GHz.
Is it possible to operate the receiver this way? My assumption is it requires the "lock to ref" mode, but I especially want to make sure the receiver will provide data output to the fabric in this mode. Also I assume the PCS should be bypassed with PCS-direct mode.
Thanks
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Hi,
Thanks for your update. I could understand your target usage. Since this is something not an intended usage of the receiver, I could not comment if the RX will be able to provide your expected data to the fabric in lock-to-ref mode. It is recommended for you to perform thorough validation using hardware to ensure it is behaving per your target application. Sorry for the inconvenience.
Please let me know if there is any concern. Thank you.
Best regards,
Chee Pin
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Hi,
As I understand it, it has been some time since I last heard from you. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.
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