User I/O conflict with DCLK (Cyclone 3)

[Altera_Forum]

I have custom board with EP3C5E144 used for educational purposes. Board contains EPCS16, SRAM and some other peripheral. 

 I create NIOS system with program stored in EPCS (it was made in accordance with solution rd11012007_792).  While compilation (fitter stage) I get Error: Cannot place I/O pin RAM_D[12] with I/O standard 3.3-V LVCMOS in pin location 11 -- possible switch coupling with I/O pin DCLK in pin location 12.  It is gone away if 1) EPCS controller removed from NIOS project or dual-purpose pins disabled for user I/O (NIOS loading from flash impossible in that case) 2) PIN_11 not used in design (it is databit of SRAM) 3) Bank 1 (where pins 11 and 12 placed) I/O standard changed to 2.5 V (my board has 3.3 V I/O)  I cannot use no one of these solutions because board is manufactured already and I want to load NIOS from EPCS.  Could anyone help me with following questions: 1) Does Altera's documents contains description of such limitation and where it can be found? 2) How I can ignore the error? WTF - error contains potential dangerous "possible switch coupling"  Thank you very much.  PS Quartus 9.0 is used

[Altera_Forum]

Hello,  

I believe your problem is that you have the default I/O voltage set to 2.5V. Try changing it to 3.3-V LVCMOS in Settings -> Device -> Device Pins & Options -> Voltage.

[Altera_Forum]

Ohh. The reason of error was found in handbook but is not wonderful :( 

   --- Quote Start ---  DCLK Pad Placement Guidelines  There is a restriction on the proximity of selected I/O standard inputs and outputs to the DCLK pin on QFP packages. The restriction is to minimize noise coupling from neighboring I/Os to the DCLK pin, and is as follows: If an I/O is using 3.0- or 3.3-V I/O standards, there must be one pad of separation between the I/O and the DCLK for QFP packages. The Quartus II software checks for this restriction.  --- Quote End ---  

[Altera_Forum]

I guess the restriction has been introduced by Altera because they observed crosstalk to DCLK. As long as the AS memory isn't operated while the RAM is active, it won't be needed however. The most simple workaround is to declare the respective I/O voltage incorrectly to 2.5V. I did this before in a design and never had to think about this issue.

[Altera_Forum]

I'm having this same issue, only I can't set the VCCIO to 2.5 - Quartus sees that I'm using an EPCS configuration device and forces the VCCIO back to 3.3, at which point I get the same thing. I'm using all of the available I/O pins on an EP3C40Q240, so I'm hoping there is a way to override this using an environment variable, and simply handle the issue logically (make sure access to the EPCS and the RAM are mutually exclusive) Is there any way to demote this to a warning?

[Altera_Forum]

--- Quote Start ---  I'm having this same issue, only I can't set the VCCIO to 2.5 - Quartus sees that I'm using an EPCS configuration device and forces the VCCIO back to 3.3, at which point I get the same thing. I'm using all of the available I/O pins on an EP3C40Q240, so I'm hoping there is a way to override this using an environment variable, and simply handle the issue logically (make sure access to the EPCS and the RAM are mutually exclusive) Is there any way to demote this to a warning?  --- Quote End ---    Try followings: 1) At "Configuration" tab of "Device and pin options" set checkbox "used configuration device" and select EPCS which you use; In the listbox below (Configuration device I/O voltage) select 2.5V If it's not help then  2) Go to "Voltage" tab and set "Default I/O standard" to 2.5V. It must help.

[Altera_Forum]

As another option, you can also set the project's configuration method to PS, but configure AS with MSEL. There are actually various methods to make your design work, you may want to try a bit.

[Altera_Forum]

one good solution is set PIN11 "I/O Maximum Toggle Rate" to "0" by Assignment Editor.