I am using a Stratix III and have 4 clocks being output from a single PLL. What I would like to do is to generate two output clocks by multiplexing clk[0] and clk[2] together for the first output clock and clk[1] and clk[3] for the second.
I have generated two clkctrl blocks with two clock inputs each and a single selection bit (where a '0' selects clk[2] or clk [3] and a '1' selects clk[0] or clk[1])). This seems to work fine, but I am getting a design assistant critical warning (Rule C101) about implementing gated clocks according to the Altera standard scheme. I have looked through the help files and megafunction user-guide, but I can't find anything along the lines of what I am trying to accomplish.
Ideally I would want to disable the output clocks based on three other input signals, so I have added in an enable signal in the mega-wizard and generated a combinatorial input for my enable based on these 3 signals. Unfortunately I still get the same warning about gated clocks, except the signals in the warning list are now the output of the clkctrl block instead of signals in my design.
Looking at the help message for this warning:
quartushelp.altera.com/9.1/mergedProjects/verify/da/comp_file_rules_clock.htm it talks about using 2-input and-gates and registering the non-clock input signal when doing clock gating, but I am not trying to do clock-gating in the FPGA fabric, and I don't see anywhere a description of how to correctly accomplish this using the CLKCTRL block without getting warnings.
If anyone has done this before or could shed any light it would be greatly appreciated.
Cheers,
Scott
