Using CPLDs as a dedicated DDC

[Altera_Forum]

Hi, 

 The have an ADC sampling at 37.4MSps and I want to fed this data into a DSP for real-time baseband processing. However, I need an interface between the ADC and DSP to digitally down converter the bandwidth of interest (6MHz at Fs/4 = 9.35MHz) to baseband, so the DSP processing load is reduced. I'll use a NCO generating a signal at Fs/4 - 9.35MHz, also generating I and Q. This shouldn't need too many resources.   I'm looking for a low cost solution (rather than using FPGA or ICs) and I am wondering if a DDC can easily be implemented by a CPLD?  There doesn't seem to be many resources online for this.   Kindest regards, Les.

[Altera_Forum]

Create a design and synthesize it in a CPLD. I'm not sure why you are using an NCO though, since it is not necessary. 

 If you are sampling a real-valued signal at 37.4MSps, then I assume you are sampling DC to 37.4/2 = 18.7MHz, or a Nyquist zone above that.  To mix that signal to complex-valued baseband you can use a complex-valued exponential at fs/4, which is just 1, -j, -1, +j.   Assuming your ADC output format is 2's compliment, and that you saturate your most-negative value to -2^(B-1)+1, which is the negative of the most positive value +2^(B-1)-1, then you can simply rearrange the real-valued data into a complex-valued data stream.  But mixing to complex-valued baseband is only half the DSP task, your real question should be "how much logic does my decimation filter require"? Since you need to low-pass filter that complex-valued data and decimate to create the signal you expect to pass to the DSP (the mixing/filtering/decimation could all be implemented by a single multi-rate filter). The "complexity" and hence resource requirements of that filter depend on how much signal there is in the band you want the DSP to process.   You state above that your signal of interest has a bandwidth of 6MHz, is that +/-6MHz, or +/-3MHz? If its the latter, then you can decimate your signal quite a lot before passing it to the DSP, or you can decimate it "as much as is needed" to get the data onto the DSP. The latter option would have a faster data rate to the DSP, less decimation in the CPLD, and a decimation filter with a slower transition band, hence it would be simple (not too resource intensive). A CPLD might be able to do it, or worst-case a small FPGA. Personally I would recommend a small FPGA, as they have the benefit of on-chip memories, which are useful for the FIFOs needed for bridging across the clock domain from your ADC to your DSP, and also you can use SignalTap to capture ADC samples while debugging.  Cheers, Dave

[Altera_Forum]

Thanks for the great feedback! 

 Sorry, yes I was meaning to use +1 0 -1 then do a Hilbert transform to obtain Q. Using a complex-valued exponential looks like a very handy method. Do you know of any good references on this method? I'm not sure what you mean by "that you saturate your most-negative value to -2^(B-1)+1, which is the negative of the most positive value +2^(B-1)-1, then you can simply rearrange the real-valued data into a complex-valued data stream."  The bandwidth of interest is +/- 3MHz. Also, the channel of interest has a 25KHz BW. I'm thinking once the +/-3MHz is at baseband I can then filtering and FM demodulate the 25KHz channel in the DSP.   How do I identify the maximum amount I can decimate by? If I can work how much resources used for this then maybe I can gauge how big FPGA/CPLD I would need. The core processor of the DSP is 400MHz - I think it would be nice to decimate as much as possible to increase the instructions per cycle in the DSP. but as you say decimating "as much as is needed", I can use less resources in the CPLD/FPGA. This will require optimization methods.   Do you have any suggestion on selecting a FPGA for the DDC? Many thanks in advance.  Cheers, Les.

[Altera_Forum]

--- Quote Start ---   Sorry, yes I was meaning to use +1 0 -1 then do a Hilbert transform to obtain Q.   --- Quote End ---   Hilbert transforms don't always have a good frequency response across the whole band, however, in your case, your signal bandwidth is fairly small compared to your sampled bandwidth, so it might be ok. I'd compare both methods and select the one that works best.    --- Quote Start ---   Using a complex-valued exponential looks like a very handy method. Do you know of any good references on this method?   --- Quote End ---   Sure, look at these (there's references to books etc)  http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc-104paper_hawkins.pdf http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc-104slides_hawkins.pdf http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc-104code_hawkins.zip    --- Quote Start ---   I'm not sure what you mean by "that you saturate your most-negative value to -2^(B-1)+1, which is the negative of the most positive value +2^(B-1)-1, then you can simply rearrange the real-valued data into a complex-valued data stream."   --- Quote End ---   A B-bit number in 2's compliment format has the range -2^(B-1) to 2^(B-1)-1, eg., B = 8-bits can represent -128 to 127. If you demodulate that using +/-1 and +/-j, what do you do with -(-128) = +128? This is a 9-bit 2's compliment number, so negation has caused an unnecessary bit-growth of 1-bit. A "better" solution is to look at the ADC samples and replace every sample equal to -128 with -127. That results in an ADC data stream that is "signed symmetric", and allows you to simply flip the sign in the demodulation, eg., -(-127) = +127, without any bit-growth. This does not increase quantization noise, since you have already saturated the most-positive signal to +127.    --- Quote Start ---   The bandwidth of interest is +/- 3MHz. Also, the channel of interest has a 25KHz BW. I'm thinking once the +/-3MHz is at baseband I can then filtering and FM demodulate the 25KHz channel in the DSP.    --- Quote End ---   Then depending on whether you decide to just preserve the channel, or the full 3MHz, your FIR filter can have a very slow transition, so it will require fewer coefficients, and be simpler to implement. The filter will also have less bit-growth, so the data width going to the DSP will not get too large.    --- Quote Start ---   How do I identify the maximum amount I can decimate by?   --- Quote End ---   By designing the filter :) Seriously though, use a package like MATLAB or Octave, decide what your transition bandwidth, passband ripple, and stop-band requirements are, and design a couple of filters.    --- Quote Start ---   If I can work how much resources used for this then maybe I can gauge how big FPGA/CPLD I would need.   --- Quote End ---   First determine what the maximum sustained transfer rate from your FPGA to CPLD is; that will be your system bottleneck.    --- Quote Start ---   The core processor of the DSP is 400MHz - I think it would be nice to decimate as much as possible to increase the instructions per cycle in the DSP. but as you say decimating "as much as is needed", I can use less resources in the CPLD/FPGA. This will require optimization methods.    --- Quote End ---   It depends on whether you like writing software or hardware :) Personally I would "optimize" to have the FPGA do it all. Then there is no ambiguity in performance.    --- Quote Start ---   Do you have any suggestion on selecting a FPGA for the DDC? Many thanks in advance.   --- Quote End ---   The references above will help get you started.  Don't be afraid to start coding. Write some MATLAB/Octave code. Write some HDL code and some DSP code. Get an idea of what the performance of each is, and then you'll have a much better sense of where you want the code to run.  Cheers, Dave

[Altera_Forum]

Hey Les, 

 Here's an example of what is feasible (calculated using MATLAB's FDAtool);  1) ADC input Fs = 37.4MSps, 16-bit samples  2) Decimation-by-2  Low-pass filter passband = DC to 3MHz, 0.1dB passband ripple, stopband at 37.4/2-3 = 15.7MHz, 90dB stopband rejection.   9 filter coefficients required. The four either side of the center are identical, so there are 5 unique coefficients.  3) Decimation-by-4  Low-pass filter passband = DC to 3MHz, 0.1dB passband ripple, stopband at 37.4/4-3 = 6.35MHz, 90dB stopband rejection.   44 coefficients required. The coefficients are symmetric, so 22 unique values.  Because FPGAs can operate at >100MHz, both of these filters can probably be implemented using only one or two hardware multipliers. Implementing this type of DSP using an FPGA makes life easier, since it has memory to store the ADC samples, while the multiplier operates at a higher clock frequency and processes the data.  Cheers, Dave

[Altera_Forum]

Great examples! and thanks for the references. 

 I like the idea of implementing all DDC DSP in a FPGA ie complex-valued baseband (mixing fs/4 = 9.35MHz) and decimation filter (by 4). I would like decide on a FPGA family and size for this.  I had FDAtool simulating a few different filter designs. As you discussed, if I used a decimate-by-4 filter it would requires 44 coefficients. Is there a method that relates the filter coefficients to the FPGA resources required?  Cheers, Les.

[Altera_Forum]

--- Quote Start ---   I would like decide on a FPGA family and size for this.   --- Quote End ---   I think a Cyclone IV would probably work. The resources required depend on your ADC bit-width and the stop-band rejection you need to achieve, since that determines the multiplier bit-width.    --- Quote Start ---   I had FDAtool simulating a few different filter designs. As you discussed, if I used a decimate-by-4 filter it would requires 44 coefficients. Is there a method that relates the filter coefficients to the FPGA resources required?   --- Quote End ---   It depends on the filter structure. Given that your decimated data rate is a lot lower than your FPGA clock rate, fewer than 44 multipliers will be used. Altera has an FIR compiler that you can try to use, otherwise try and implement a few filters yourself. You can always get one example working, use that to select the FPGA, and then "optimize" the implementation later.  Cheers, Dave

[Altera_Forum]

--- Quote Start ---   I think a Cyclone IV would probably work. The resources required depend on your ADC bit-width and the stop-band rejection you need to achieve, since that determines the multiplier bit-width.   --- Quote End ---    I am using a 12-bit ADC. Also, given I would need around 44 multipliers would you suggest using something like the ep4ce15 (http://www.altera.com/literature/hb/cyclone-iv/cyiv-51001.pdf) (56 multipliers). These FPGAs are >$20 :eek:. I am hoping to use an FPGA around the $10 mark. It looks like I may need to use wider transition bands for filtering if I want an FPGA around this price.  Cheers, Les.

[Altera_Forum]

--- Quote Start ---  I am using a 12-bit ADC   --- Quote End ---   Ok. FPGA multipliers increment in steps of 9-bits, so you'll likely end up using an 18-bit multiplier.    --- Quote Start ---   Also, given I would need around 44 multipliers   --- Quote End ---   The filter has 44 coefficients. This does not mean 44 multipliers. For a start, the coefficients are symmetric, so that halves the number of multipliers you would use if you implemented an FIR at the same rate as the ADC data. However, once you are decimating data, you are in "multi-rate" territory, where your FIR filter can reuse an FPGA DSP block operating at a higher frequency than your data rate.  Do a little more work figuring out the filter logic first, and then look at the FPGA.  Cheers, Dave