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Valued Contributor III
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Using HIP PCIe from Cyclone V Development board to communicate to PC

I am trying to implement HIP PCIe in Cyclone V development board to communicate with a PC. In PC I have jungo driver installed. 

 

In QSYS, I have instantiated: 

1. PCIe_1x4 (Avalon Memory mapped) with one BAR (BAR0) set to 32-bit non-prefetchable memory and using 100 MHz. From this block, I have exported the following signals: refcllk, npor, hip_ctrl, reconfig_clk_locked, hip_serial, and hip_pipe. But the signal Txs is not connected to any where. The rest of the signals are: Rxm_BAR0, reconfig_to_xcvr, reconfig_busy, reconfig_from_xcvr and cra are connected to other blocks. 

 

2. Transceiver Reconfiguration controller with number of reconfiguration interfaces: 5. reconfig_busy, mgmt_clk_clk, mgmt_rst_reset, reconfig_to_xcvr, and reconfig_from_xcvr are connected to other blocks and reconfig_mgmt is exported (it is not used any where) 

 

 

  1. Clock source with 125 MHz taking from the development board (Y15 and AA15 diff pair) and clk_in_reset, I have assigned '1' (assuming always out of reset) to it at the top level.  

 

 

4. PIO (Parallel I/O) with 32 bits as output. 

 

Following are my connections: 

 

  1. refclk from PCIe core is connected to pin W8 and, W7, which are differential pair from PC.  

  2. coreclkout from PCIe core is feeding PIO clk.  

  3. nreset_status from PCIe core is feeding PIIO reset.  

  4. Rxm_BAR0 from PCIe core from PCIe is feeding Txs and cra in PCIe core also feeding PIO s1.  

  5. reconfig_busy from XCVR_Reconfig is feeding reconfig_busy in PCIe core.  

  6. reconfig_to_xcvr from XCVR_Reconfig is feeding reconfig_to_xcvr in PCIe core.  

  7. reconfig_from_xcvr from XCVR_Reconfig is feeding reconfig_from_xcvr in PCIe core.  

  8. clk from clock source is feeding mgmt_clk_clk in XCVR_Reconfig.  

  9. clk_reset from clock source is feeding mgmt_rst_reset in XCVR_Recnfig.  

 

 

I have generated the synthesis files and complied the code. When I download the sof file into FPGa in the development board there was no problem. Also using Jungo driver, I am able to see Altera device with VID 1172. Jungo driver can identify any changes I do between sof files. 

 

But when I use Read/Write using address value for PIO base register (2000), Read returns FFFFFFFF and I I write different value to the same location re-read returns FFFFFF. 

 

Does anybody know what am I doing wrong here? 

 

Thank you all.
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