Using OpenCore Plus IP (Triple Speed Ethernet) in Quartus v13.0 subscription edition

[Altera_Forum]

I was given a Quartus II project that makes use of Altera's Triple-Speed Ethernet MegaCore Function IP. The project was originally written in Quartus II v13.0 (subscription edition). I have the same version of Quartus II (a 1-year license came with my Cyclone V GT development kit).  

 When I compile the project, the Analysis & Synthesis, Fitter, Assembler, and Timing Analysis all succeed. But the EDA Netlist Writer fails. I get 2 classes of errors:  Ones like this: Error (204009): Can't generate netlist output files because the license for encrypted file "C:/path/to/project/TSE_RGMII/altera_tse_tx_min_ff.v" is not available  And others like this: Error (204012): Can't generate netlist output files because the file "C:/path/to/project/TSE_RGMII/altera_tse_tx_min_ff.v" is an OpenCore Plus time-limited file   If I understand correctly, OpenCore Plus IP don't require licenses for evaluation (I know that some OpenCore IP requires tethering, while others will run untethered for some finite amount of time -- though I've not been able to find documentation about the tethering/timeout specs for a given IP). So I'm confused by the first error message that suggests a license *is* needed.  How do I tell Quartus to use the OpenCore IP? I began to use the MegaWizard Plug-In Manager, but it seems to me that this would just re-generate the code that already lives in the TSE_RGMII/ sub-directory of my project.  Many thanks

[Altera_Forum]

As simple as that: You can't. 

 OpenCore License is automatically used if there is no valid license for the IP core. OpenCore License allows you to evaluate the IP on your board. Also (most) of the IP cores have functional models for simulation but at least generating the netlist for third party tools is not allowed. I am not that into details, but I think if you could create the complete design for a third party simulator at rtl or gate level, you could also simply copy the IP core out of it. On Altera website the workaround for this is to simply deactivate the EDA Netlist step at compilation

[Altera_Forum]

Correct. 

 You are NOT able to generate EDA-Netlists, but functional FPGA-Image.  Please have a deeper look into [1] and [2] for further questions.  [1] https://www.altera.com/support/support-resources/download/megacore-ip.html [2] https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/an/an320.pdf  Regards

[Altera_Forum]

I see -- thanks for clarifying. I also found this page helpful: 

https://www.altera.com/support/support-resources/knowledge-base/solutions/rd12202011_654.html  which specifies how to deactivate the EDA Netlist step in the compilation:   --- Quote Start ---  To avoid this error, disable the EDA simulation tool in your project by opening the Settings dialog box from the Quartus II Assignments menu. Select the category EDA Tool Settings and the subcategory Simulation. On the Simulation page of the Settings dialog box, change the Tool name option to <None>.  --- Quote End ---    For reference, I found that Triple-Speed Ethernet is part of the MegaCore IP library and that   --- Quote Start ---  For MegaCore functions, the untethered timeout is 1 hour; the tethered timeout value  is indefinite  --- Quote End ---   (from https://www.altera.com/en_us/pdfs/literature/ug/ug_ed8b10b.pdf)