Using Quartus II to find Fmax with only 1 register in the circuit

[Altera_Forum]

I am trying to determine the Fmax in a circuit that only consists of a single register, placed at some point between the inputs and outputs.  

Is it possible to measure the Fmax for the IO-register and register-IO paths? If so, how?  Thanks in advance!

[Altera_Forum]

Fmax is register to register, so it doesn't really exist with a single register. You have an external device that sends the data, and an external device that receives it, so it's a matter of putting in those external delays. Maybe look at the first chapter of the TImeQuest User Guide on alterawiki.com, which covers I/O constraints. 

 That being said, I assume you want something more complicated. Why just bring in a data signal, register, and send it back out. Minimally I assume there should be some logic with it, which changes things.

[Altera_Forum]

Thanks for the reply!  

 Actually, you were right and I was simply not being specific enough - there is some simple logic involved before and after the register. But wouldn't this not affect my ability to measure some sort of critical delay within the circuit?

[Altera_Forum]

That logic affects the timing as much as anything else, so you want those delays in there. You won't get a data sheet number for this, you will need to create the design, select a pinout and enter timing constraints, as all of those things affect the timing. This will not run very fast. To get even moderate speeds users generally register the input and output of their design. (Everyone has a different meaning for fast, so hard to say...)

[Altera_Forum]

Okay, maybe I am confusing myself or not properly understanding your explanation.  

Say I have given a timing constraint for the circuit, appropriate inputs, outputs, arbitrary logic and a single register in the middle of the entire circuit and want to find the critical delay within the circuit.  This circuit is, in theory, "isolated" and I am looking to estimate the Fmax or critical delay of the circuit (e.g. from the input pin to the register or from the register to the output pin). In this case, external delays are not known, which is why I may be getting confused.

[Altera_Forum]

So the logic plays decent part of the delay and can't be ignored. But let's say there is an input pin and an output pin. The fitter can put the register closer to the input or the output, dependent on requirements, so it's not a fixed value. Now, you would probably lay out the board so the pins are close to each other, so it's not too big of a trade-off(as opposed to being on opposite sides of the die), but still substantial. If your clock goes through a PLL, then you can change the delay to the register, which could probably have a bigger effect. For example, without any compensation the clock delay to the register could be 3-4ns, which makes your clock to output 3-4ns worse, but your setup time 3-4ns better. You could phase-shift the clock forward or backward and make trade-offs between the input and output. It's just not something you can determine without knowing the whole problem. What frequency are you trying to run at? What device?

[Altera_Forum]

If you are aiming for the highest possible clock rate on an input/logic/output path, then you should use the Altera FPGA capability that embeds a register in the input cell, and the output cell. This provides that lowest delay possible for input pad to clocked register, and clocked register to output pad. Then you can use anywhere from zero to N registers in the core to clock data in a pipeline.