Using Virtual JTAG interface as additional input

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

Using Virtual JTAG interface as additional input

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Helo there,

let say i have block design with input X , and output Y.

To save IO, i'm planning to use the Virtual JTAG.

my intend is that,

when assign Y = load_mdio? tdo_sig: tdi_sig; //bypass

assign X = load_mdio? tdi_sig :1'bz; //tristate

load_mdio = ir_in_sig[1] && ~ir_in_sig[0];

1) Will this work?

2) with this setup, I'm assuming that all I have to do is set ir_in_sig=2'b10 , and my internal X,Y should be working like any other pins at TDI/TDO?

3) I don't havethe hardware to test this yet , after I program the ir_in_sig via JTAG cable (Quartus_stp), can i disconnect the cable and use TDI/TDI for other purpose as i wanted?

thanks for your help.

rgds,

cellv

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