Using a PLL to synchronize two clocks

[Altera_Forum]

Hello, 

 I have a 120 MHz external clock entering the FPGA (Stratix II). Part of the interface in the FPGA must work at the 120 MHz, but most of it (including a Nios CPU) works at 60 MHz. The 60 MHz clock is generated by dividing the main 120 MHz clock using a PLL.  Can I use the zero-delay feature of the PLL to make sure that the rising edges of the two clocks are aligned, so that I can safely move signals between the two domains without synchronizing in a 2-stage DFF? (assuming the speed difference is not a problem).  Thanks in advance

[Altera_Forum]

You can do it that way. Then use Timequest to ensure that the setup and holds are ok in the two domains. Ensure that the two clocks are in the same group so that Timequest analyses the transfers between the two domains. You may have to specify some multicycle transfers, but you can start without them and see what Timequest says.

[Altera_Forum]

What's the source for these two clocks? Ideally you would have one clock come in and create both the 120 and 60 MHz clocks. Then everything works out(and TimeQuest will do what you want.) You don't even have to do Zero Delay Buffer. 

It gets more confusing if they're two different clocks coming into the device, because you'll need to determine and phase difference and jitter between the external clocks and put that into your TimeQuest. If you explain the setup, there might be some more things to account for.

[Altera_Forum]

--- Quote Start ---  What's the source for these two clocks? Ideally you would have one clock come in and create both the 120 and 60 MHz clocks. Then everything works out(and TimeQuest will do what you want.) You don't even have to do Zero Delay Buffer. It gets more confusing if they're two different clocks coming into the device, because you'll need to determine and phase difference and jitter between the external clocks and put that into your TimeQuest. If you explain the setup, there might be some more things to account for.  --- Quote End ---     The source of the 120 MHz one is external. The 60 MHz one I want to create from the 120 MHz one.   I can probably create two clocks from the 120: one 120 and another 60, and make them phase-aligned. Is this true?

[Altera_Forum]

Yes, create a PLL with two outputs of 120Mhz and 60MHz. Everything will be taken care of for you. No reason to do Zero Delay Buffer either, and you can leave it in Normal mode.

[Altera_Forum]

--- Quote Start ---  Yes, create a PLL with two outputs of 120Mhz and 60MHz. Everything will be taken care of for you. No reason to do Zero Delay Buffer either, and you can leave it in Normal mode.  --- Quote End ---    So the two clocks generated by the same PLL and are a multiple of one another (two of C1..C6, IIRC) are guaranteed to be phase aligned? Does the PLL have to be enhanced for that, or will a fast PLL do the same?

[Altera_Forum]

Yes. They may not be down to the exact picosecond, but adding: 

derive_clock_uncertainty  to your .sdc file(assuming you're targeting 65nm or newer devices) will add a little uncertainty to these transfers to account for this. (If you're using the Classic Timing Analyzer or parts older than 65nm, the uncertainty is built into the model). For the record, a majority of designs do exactly what you're doing, so don't worry about it.

[Altera_Forum]

OK, Daixiwen and Rysc thanks a lot for your replies.