Hello!
It is well-known that at the beginnig of a FPGA powering-up sequence there is an inrush current. So, it is written in the
stratix v device handbook that power should ramp-up monotonically without any plateaus to avoid POR event. But due to this big initial current there occurs some spikes on a power rail output (for example a PoL DC-DC). It can cause some instability in ramping-up of the power and as a sequence POR event appearing. Conventionally, this inrush current is made monotonic by output capacitors and inductors.
But recently I have found in the
stratix v device handbook p8-5 this text
--- Quote Start ---
Power up all the power supplies that are monitored by the POR circuitry. All power supplies, includingVCCPGM and VCCPD, must ramp up from 0 V to the recommended operating voltage level within theramp-up time specification. Otherwise, hold the nCONFIG pin low until all the power supplies reach therecommended voltage level.
--- Quote End ---
So, does it mean that I can hold down nCONFIG until all desired voltage level is reached to avoid getting POR event? Does it mean that I can remove most of the capacitors between a point-of-load and Vcc pins?
Thank you very much
