VHDL 2008 vs System Verilog

[Altera_Forum]

I have been using VHDL 2008 for several months now and like the new features of the language. In particular, I use Active-HDL and the VHDL 2008 language constructs are all fully supported. There is a subset of features supported by Quartus. One of the features not supported by Quartus is the general unconstrained type, although Quartus supports unconstrained arrays. Interestingly enough, many of the features of system verilog have been implemented by Quartus . . . which got me looking into the lanugage. In my career, I have written about 10% Verilog, 90% VHDL. For control engineering, VHDL has worked well, with arithmetic operands and filter implementations, etc. However, System Verilog appears to have many VHDL features, with some very nice "data typing" capabilities borrowed from C, such as struct and union. It appears that struct and union are a tad bit more flexible than the VHDL record type, which is also quite flexible. It is just that System Verilog is "ahead" in synthesis features with Quartus. I am wondering if Altera sees this as a long trajectory for development? i.e. system verilog synthesis being ahead of VHDL 2008?  

 In short, the VHDL data type "record" is one that I most often, and makes code very readable. The use of the generic data types is one "key" ingredient in selecting language use.   Consider, for example:  type counterType is record   done : std_logic;  enable: std_logic;  reset : std_logic; end record; signal counter : counterType; signal counter2: counterType;  Makes possible writing code like this:   -----------------------*/ FSM: process(all) begin if HRST then  state <= S0;  recloser.tries <= 0;   FaultOut <= '0';  counter.reset <= '0';  counter.enable <= '0'; elsif rising_edge(MCLK) then  case state is    when S0 =>  if ENABLE and desatCondition then  if recloser.tries < PARAM_RECLOSER_COUNTS then  state <= S1;  counter.reset <= '1';  recloser.tries <= recloser.tries + 1;  else  state <= FAULT;  counter.reset <= '0';  end if;  elsif ENABLE and refresh then   state <= S0;  counter.reset <= '1';  recloser.tries <= 0;  and alos "clustering" control signals around modules to make them easier to handle, such as:  --/* ---------------------------------------- -- Delay counter between recloser tries --------------------------------------------*/ U3: entity work.DNCNT_INTEGER(BEH)  generic map (  size => PARAM_RECLOSER_WAIT_COUNTS+1  )  port map (  CLK => MCLK,  HRST => counter.reset,  ENABLE => counter.enable,  CNT_VALUE => PARAM_RECLOSER_WAIT_COUNTS,  FLAG => counter.done  );    Thanks, James

[Altera_Forum]

Is there a point to this post?  

From what I have heard, better 2008 support (well, theres not alot at the moment) is coming in Q12.1, with Q12 due to hit around mid 2012, so theres going to be a bit of a wait yet. I also understand that verilog/SV has a much larger user base (all internal altera development is Verilog), hence the much greater support for it.   I dont understand what you mean by your reference to "general unconstrained type"? IIRC, the only unconstrained things that 2008 allows are unconstrained array elements, and unconstrained definitions in a record type.  From the code you posted, I dont see any 2008 features in it. It all looks 1993 compatible (apart from the process(all), which IMO allows for more lazy coding than being a useful feature) )

[Altera_Forum]

--- Quote Start ---  Is there a point to this post?  From what I have heard, better 2008 support (well, theres not alot at the moment) is coming in Q12.1, with Q12 due to hit around mid 2012, so theres going to be a bit of a wait yet. I also understand that verilog/SV has a much larger user base (all internal altera development is Verilog), hence the much greater support for it.   I dont understand what you mean by your reference to "general unconstrained type"?   --- Quote End ---    --> To be more specific, a general unconstrained type is that which is described by Lewis and Ashendon, in "VHDL 2008 Just the New Stuff" such as on pages 103-107 is what I am talking about. I couldn't get code such as what is below to synthesize in Quartus . . .  type M_unconstrained is  array (natural range <>, natural range <>) of bit;  type R_unconstrained is record  e2 : M_unconstrained;  e3 : bit; end record R_unconstrained;    --- Quote Start ---     IIRC, the only unconstrained things that 2008 allows are unconstrained array elements, and unconstrained definitions in a record type.  From the code you posted, I dont see any 2008 features in it. It all looks 1993 compatible (apart from the process(all), which IMO allows for more lazy coding than being a useful feature) )  --- Quote End ---  --> process(all) is only possible with VHDL2008  James

[Altera_Forum]

The "point" to my post is that Quartus currently has better support for System Verilog than VHDL 2008, enabling the use of more advanced data structures.

[Altera_Forum]

I suggest you make a mysupport request because altera dont monitor the forum much.

[Altera_Forum]

Thanks, will make a mysupport request.