VHDL Error 10779

[GD76]

Line 434 shows the error in file spi_if.vhd.

Error (10779): VHDL error at spi_if.vhd(434): expression is not constant
Error (10658): VHDL Operator error at spi_if.vhd(434): failed to evaluate call to operator ""&""
Error (12152): Can't elaborate user hierarchy "spi_if:spi_if_i"
Error: Quartus Prime Analysis & Synthesis was unsuccessful. 3 errors, 10 warnings
Error: Peak virtual memory: 4845 megabytes
Error: Processing ended: Thu Feb 03 14:07:58 2022
Error: Elapsed time: 00:00:09
Error: Total CPU time (on all processors): 00:00:16
Error (293001): Quartus Prime Full Compilation was unsuccessful. 5 errors, 10 warnings

I have std_logic_vector passed to create XFER_SIZE and dwitdth. Not sure why the error is.

[ShengN_Intel]

Hi,

I'm able to compile spi_if.vhd successfully on my side. Try go to Assignments/Settings/VHDL Input, makes sure VHDL 2008 is selected.

Version: Quartus Prime Std 21.1

Best regards,
Sheng

[ShengN_Intel]

Hi,

Any update on this thread or Should I consider that case to be closed?

Best regards,
Sheng

[GD76]

You can close this. I have global settings for VHDL 2008 compilation anyway. It turns out Quartus Std 2018 has the limitation to synthesize but 2019 Pro edition do not.