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Novice
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VHDL FIR uses verilog fifo in simulaion model

I created a VHDL FIR using Quartus. It will not simulate because they use a verilog FIFO in there simulation Model
ELBREAD: Error: You do not have a valid license to simulate Verilog module 'brigantine.altera_avalon_sc_fifo'. Contact Aldec for ordering information - sales@aldec.com.
do I need a seperate license?

How can I get vhdl model in simulation

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Novice
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I am using Quartus version 18.1. I am simulating in Aldec Active HDL 10.5a fpr VHDL. when I created a FIR using FIRII.  The synthesis files are in VHDL, but the simulator files include altera_avalon_sc_fifo.v which cause the simulator to not simulate.  Can I get a version that has uses vhdl files only?

 

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