VHDL FIR uses verilog fifo in simulaion model

[PDone]

I created a VHDL FIR using Quartus. It will not simulate because they use a verilog FIFO in there simulation Model
ELBREAD: Error: You do not have a valid license to simulate Verilog module 'brigantine.altera_avalon_sc_fifo'. Contact Aldec for ordering information - sales@aldec.com.
do I need a seperate license?

How can I get vhdl model in simulation

[PDone]

I am using Quartus version 18.1. I am simulating in Aldec Active HDL 10.5a fpr VHDL. when I created a FIR using FIRII.  The synthesis files are in VHDL, but the simulator files include altera_avalon_sc_fifo.v which cause the simulator to not simulate.  Can I get a version that has uses vhdl files only?

[RichardTanSY_Intel]

Sorry for idling for some time. Do you able to solve your issue?

Regarding the license, you might need to contact Aldec personally. 

For FIR II IP, in the platform designer > Generate VHDL> simulation model > Choose VHDL to generate the simulation files for VHDL.