VHDL constant type synthesis

[Altera_Forum]

The constant type here is two-dimension data array constant which is correct when simulating in Modelsim, but is false when mearsured using oscillograph because I can't reach the inner unit of the constant from the result. 

I appreciate any suggestions.Thanks.

[Altera_Forum]

I'd suggest to explain your problem a bit more because I didn't understand anything.

[Altera_Forum]

Post some code so that you make more sense.

[Altera_Forum]

Like the sentence constant RAM:=("....","...",...), I need to reach any index I want when conditions meet. I realize it logically which is correct when simulating, but it went wrong when debug on board using oscillograph. The problem is I can't reach the index I want , or I can't see it in oscillograph

[Altera_Forum]

Im guessing that what you have synthesized is a ROM. You need to provide the correct address to the rom to access the internal values.

[Altera_Forum]

The constant syntax doesn't say anything about how the constant is actually implemented in your design. It may either mean a constant value that's used at compile time or involve ROM inference, when all prerequisites are met. The value would be accessible somehow in any case. "can't reach the index I want" sounds rather unclear. You should tell, what you are actually doing.