VHDL help, frequency Division

[Altera_Forum]

I need some help coding a 25 bit frequency divider. 

 I seriously just cant figure it out. I had to design a digital clock with a mod 6 and mod 10 counter.  everything seems to be fine, but I just cant do the frequency divider.  I used a 25 bit johnson counter but dont know how to get it to start dividing out the frequency,  help really appreciated.

[Altera_Forum]

I'll let someone else answer your specific question, but be careful when using a divided-down clock. See my posts at http://www.alteraforum.com/forum/showthread.php?t=754.

[Altera_Forum]

how would this work? does this successfully divide the 25 hz frequency from an altera board to 1 hz?? 

 thanks for your response, but this problem should be fairly simple, i mean we never really went over vhdl and now we're expected to code somethign in the language, so i dont think it should be in our realm of reach, but jesus i am having so much trouble as well as my class mates.   help appreciated.     Library IEEE; use IEEE.std_logic_1164.all;  entity Divider is  port (  CLK: in STD_LOGIC;  COUT: out STD_LOGIC  ); end Divider;   architecture Divider of Divider is   constant TIMECONST : integer := 59; --temp at 1 or 2 for simulation purposes signal count0, count1, count2, count3: integer range 0 to 1000 := 0; signal D: STD_LOGIC := '0';  begin   process (CLK)  begin  if (CLK'event and CLK = '1') then  count0 <= count0 + 1;  if (count0 = TIMECONST) then  count0 <= 0;  count1 <= count1 + 1;  elsif (count1 = TIMECONST) then  count1 <= 0;  count2 <= count2 + 1;  elsif (count2 = TIMECONST) then  count2 <= 0;  count3 <= count3 + 1;  elsif (count3 = TIMECONST) then  count3 <= 0;  D <= not D;  end if;  end if;   COUT <= D;   end process; end Divider;

[Altera_Forum]

--- Quote Start ---  [B]How would this work? does this successfully divide the 25 hz frequency from an ALTERA board to 1 hz??  --- Quote End ---     As I said before, I'll let someone else help you with actually doing the frequency division. You could try a simulation in Quartus to see whether the code you wrote produces the intended behavior.  For a course assignment, the cautions I referred you to might not matter to get something working well enough in the lab. The more reliable the solution has to be, the more those considerations matter any time you drive a clock used internal to the FPGA with logic resources as you would be doing if you drive it with a frequency divider.

[Altera_Forum]

--- Quote Start ---  As I said before, I'll let someone else help you with actually doing the frequency division. You could try a simulation in Quartus to see whether the code you wrote produces the intended behavior.  For a course assignment, the cautions I referred you to might not matter to get something working well enough in the lab. The more reliable the solution has to be, the more those considerations matter any time you drive a clock used internal to the FPGA with logic resources as you would be doing if you drive it with a frequency divider.  --- Quote End ---    wah wah wah   :(

[Altera_Forum]

please find below a link and i think this will help you out  

 http://www.freeinfosociety.com/site.php?postnum=521  let me know if this is clear .    regards,  Sreeram