VHDL ili9341 configuration

Manzy · ‎02-12-2025

this is the lcd ili9341 screen im trying to configure with VHDL for project, ill add here in the end the modules i built. i created an SPI module and ili configuration module by looking at the data sheet and inspecting another modules online, i find it dificult to configure it with the configurations i have found, also i have tried to work with lower system clk for the SCK around 10MHZ so the system would not exeed the system clock that should be maximum 24MHZ. please someone could help me find a way to configure it and explain to me the process of showing data over the screen.

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.NUMERIC_STD.ALL;

entity ili9341_spi is

Port (

spiClk : in std_logic; -- Input clock signal for SPI timing 12Mhz

data : in std_logic_vector(8 downto 0); -- 9-bit data to be transmitted (MSB is DC flag)

dataAvailable : in std_logic; -- Indicates that new data is available for transmission

tft_sck : out std_logic; -- SPI clock output to the TFT (active only when CS is active)

tft_sdi : out std_logic; -- SPI data output to the TFT (serial data line)

tft_dc : out std_logic; -- Data/Command (DC) signal for the TFT (MSB of the data)

tft_cs : out std_logic; -- Chip Select (CS) signal for the TFT (active low)

idle : buffer std_logic := '1' -- Indicates the SPI module is idle (1 when no transmission in progress)

);

end ili9341_spi;

architecture ili9341_spi_arc of ili9341_spi is

-- Registers

signal send_index : integer range 1 to 7 := 1;

signal internalData : std_logic_vector(8 downto 0) := (others => '0');

signal cs : std_logic := '1';

-- Combinational Assignments / wires

signal dataDc : std_logic;

signal dataShift : std_logic_vector(0 to 7);

begin

-- Wires Assignments

dataDc <= internalData(8);

dataShift <= internalData(7 downto 0);

-- SPI transmit

process(spiClk)

begin

if rising_edge(spiClk) then

-- Store new data in internal register

-- Having Data and ready to transmite

if dataAvailable = '1' and idle = '1' then

internalData <= data; -- Copy new data into internal buffer

idle <= '0'; -- Start transmission

cs <= '0'; -- ili9341 selected

tft_sdi <= dataShift(0);

--end if;

-- Change data if we're actively sending

elsif idle = '0' then

-- Update Pins

tft_sdi <= dataShift(send_index);

-- Increment counter

if send_index = 7 then

send_index <= 1; -- Reset send_index after sending 8bits

idle <= '1'; -- sending last bit;

else

send_index <= send_index + 1;

end if;

-- no data to send

else

cs <= '1';

end if;

end process;

-- Assigning

tft_dc <= dataDc;

tft_sck <= spiClk and not cs; -- only drive sck with an active CS

tft_cs <= cs;

end ili9341_spi_arc;

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.NUMERIC_STD.ALL;

use work.ili9341_pkg.all;

entity ili9341 is

Port (

clk : in std_logic; -- Input clock (e.g., 100MHz)

tft_sck : out std_logic; -- SPI clock signal

tft_sdi : out std_logic; -- SPI data output (MOSI)

tft_dc : out std_logic; -- Data/Command signal

tft_reset : out std_logic; -- Reset signal for the TFT (active low)

tft_cs : out std_logic; -- Chip Select (active low)

-- framebufferData : in std_logic_vector(15 downto 0):=x"00"; -- RGB565 data input for the frame buffer

led : out std_logic_vector(3 downto 0);

framebufferClk : out std_logic -- Framebuffer clock to synchronize data reading

);

end ili9341;

architecture ili9341_arc of ili9341 is

-- Constant

constant INPUT_CLK_MHZ : integer := 24;

-- Signals

signal spiClk : std_logic := '0'; -- Generated 10-12MHz clk

signal spi_counter_clk : integer range 0 to 10 := 0; -- Counter For spiClk

signal frameBufferLowNibble : std_logic := '1';

signal spiData : std_logic_vector(8 downto 0) := (others => '0'); -- Data to send via SPI

signal spiDataSet : std_logic := '0'; -- Indicates new data is ready

signal spiIdle : std_logic := '1'; -- Indicates SPI is idle

component ili9341_spi